Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | riscv: Implement sv48 support | Alexandre Ghiti | 2022-01-19 | 1 | -2/+2 |
* | riscv: mm: don't advertise 1 num_asid for 0 asid bits | Vineet Gupta | 2021-10-04 | 1 | -3/+5 |
* | riscv: add ASID-based tlbflushing methods | Guo Ren | 2021-06-30 | 1 | -1/+1 |
* | riscv: mm: Use better bitmap_zalloc() | Kefeng Wang | 2021-06-08 | 1 | -2/+1 |
* | riscv: Add __init section marker to some functions again | Jisheng Zhang | 2021-05-29 | 1 | -1/+1 |
* | riscv: Optimize switch_mm by passing "cpu" to flush_icache_deferred() | Jisheng Zhang | 2021-05-25 | 1 | -3/+4 |
* | RISC-V: Implement ASID allocator | Anup Patel | 2021-02-18 | 1 | -4/+261 |
* | riscv: add nommu support | Christoph Hellwig | 2019-11-17 | 1 | -0/+2 |
* | riscv: add missing header file includes | Paul Walmsley | 2019-10-28 | 1 | -0/+1 |
* | riscv: Using CSR numbers to access CSRs | Bin Meng | 2019-08-30 | 1 | -6/+1 |
* | riscv: move switch_mm to its own file | Gary Guo | 2019-05-16 | 1 | -0/+69 |