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path: root/arch/riscv/mm/tlbflush.c
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* Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2024-05-221-54/+21
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| * riscv: mm: Always use an ASID to flush mm contextsSamuel Holland2024-04-291-2/+1
| * riscv: mm: Introduce cntx2asid/cntx2version helper macrosSamuel Holland2024-04-291-1/+1
| * riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Samuel Holland2024-04-291-1/+1
| * riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vmaSamuel Holland2024-04-291-23/+0
| * riscv: Only send remote fences when some other CPU is onlineSamuel Holland2024-04-291-1/+3
| * riscv: mm: Broadcast kernel TLB flushes only when neededSamuel Holland2024-04-291-13/+5
| * riscv: Use IPIs for remote cache/TLB flushes by defaultSamuel Holland2024-04-291-17/+14
* | riscv: mm: Fix prototype to avoid discarding constSamuel Holland2024-03-261-2/+2
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* riscv: Fix arch_tlbbatch_flush() by clearing the batch cpumaskAlexandre Ghiti2024-02-071-0/+1
* riscv: mm: execute local TLB flush after populating vmemmapVincent Chen2024-01-311-1/+2
* Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2024-01-201-20/+49
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| * riscv: Add support for BATCHED_UNMAP_TLB_FLUSHAlexandre Ghiti2024-01-111-20/+49
* | mm: Introduce flush_cache_vmap_early()Alexandre Ghiti2023-12-141-0/+5
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* riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti2023-11-061-10/+24
* riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti2023-11-061-56/+59
* riscv: Improve flush_tlb_range() for hugetlb pagesAlexandre Ghiti2023-11-061-1/+28
* riscv: Improve tlb_flush()Alexandre Ghiti2023-11-061-0/+7
* RISC-V: Use IPIs for remote TLB flush when possibleAnup Patel2023-04-081-15/+78
* riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong2023-03-211-1/+1
* Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich2023-03-091-11/+17
* riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich2022-12-081-17/+11
* RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra2022-01-201-7/+2
* riscv: add ASID-based tlbflushing methodsGuo Ren2021-06-301-7/+40
* riscv: pass the mm_struct to __sbi_tlb_flush_rangeChristoph Hellwig2021-06-301-9/+6
* riscv: mm: add THP support on 64-bitNanyong Sun2021-05-221-0/+7
* riscv: mm: add param stride for __sbi_tlb_flush_rangeNanyong Sun2021-05-221-5/+5
* RISC-V: Issue a tlb page flush if possibleAtish Patra2019-10-291-1/+4
* RISC-V: Issue a local tlbflush if possible.Atish Patra2019-10-291-2/+17
* RISC-V: Do not invoke SBI call if cpumask is emptyAtish Patra2019-10-291-0/+3
* riscv: move the TLB flush logic out of lineChristoph Hellwig2019-09-051-0/+35
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