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* Merge remote-tracking branch 'riscv/riscv-wx-mappings' into fixesPalmer Dabbelt2021-06-011-2/+6
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| * riscv: mm: Fix W+X mappings at bootJisheng Zhang2021-06-011-2/+6
* | RISC-V: Fix memblock_free() usages in init_resources()Wende Tan2021-06-011-2/+2
* | riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent2021-06-011-1/+1
* | riscv: Use -mno-relax when using lld linkerKhem Raj2021-05-291-0/+9
* | riscv: kexec: Fix W=1 build warningsJisheng Zhang2021-05-222-7/+8
* | riscv: kprobes: Fix build error when MMU=nJisheng Zhang2021-05-221-0/+2
* | riscv: Select ARCH_USE_MEMTESTKefeng Wang2021-05-221-0/+1
* | riscv: stacktrace: fix the riscv stacktrace when CONFIG_FRAME_POINTER enabledChen Huang2021-05-221-7/+7
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* riscv: remove unused handle_exception symbolRouven Czerwinski2021-05-061-2/+0
* riscv: Consistify protect_kernel_linear_mapping_text_rodata() useGeert Uytterhoeven2021-05-063-4/+7
* riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=yVincent Chen2021-05-061-2/+2
* riscv: Only extend kernel reservation if mapped read-onlyGeert Uytterhoeven2021-05-061-2/+7
* Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-05-0663-214/+2525
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| * RISC-V: Always define XIP_FIXUPPalmer Dabbelt2021-05-011-10/+13
| * riscv: Remove 32b kernel mapping from page table dumpAlexandre Ghiti2021-05-011-3/+3
| * riscv: Fix 32b kernel build with CONFIG_DEBUG_VIRTUAL=yAlexandre Ghiti2021-05-011-1/+1
| * RISC-V: Fix error code returned by riscv_hartid_to_cpuid()Anup Patel2021-05-011-1/+1
| * RISC-V: Enable Microchip PolarFire ICICLE SoCAtish Patra2021-04-261-0/+4
| * RISC-V: Initial DTS for Microchip ICICLE boardAtish Patra2021-04-264-0/+404
| * RISC-V: Add Microchip PolarFire SoC kconfig optionAtish Patra2021-04-261-0/+7
| * RISC-V: enable XIPVitaly Wool2021-04-2611-19/+424
| * RISC-V: Add crash kernel supportNick Kossifidis2021-04-265-0/+102
| * RISC-V: Add kdump supportNick Kossifidis2021-04-268-27/+249
| * RISC-V: Improve init_resources()Nick Kossifidis2021-04-261-44/+46
| * RISC-V: Add kexec supportNick Kossifidis2021-04-265-0/+412
| * riscv: vdso: fix and clean-up MakefileJisheng Zhang2021-04-261-2/+2
| * riscv/mm: Use BUG_ON instead of if condition followed by BUG.zhouchuangao2021-04-261-2/+2
| * riscv/kprobe: fix kernel panic when invoking sys_read traced by kprobeLiao Chang2021-04-261-1/+3
| * riscv: Set ARCH_HAS_STRICT_MODULE_RWX if MMUJisheng Zhang2021-04-261-0/+1
| * riscv: module: Create module allocations without exec permissionsJisheng Zhang2021-04-261-1/+1
| * riscv: bpf: Avoid breaking W^XJisheng Zhang2021-04-261-1/+2
| * riscv: bpf: Move bpf_jit_alloc_exec() and bpf_jit_free_exec() to coreJisheng Zhang2021-04-262-13/+13
| * riscv: kprobes: Implement alloc_insn_page()Jisheng Zhang2021-04-261-0/+8
| * riscv: Constify sbi_ipi_opsJisheng Zhang2021-04-263-5/+5
| * riscv: Constify sys_call_tableJisheng Zhang2021-04-262-2/+2
| * riscv: Mark some global variables __ro_after_initJisheng Zhang2021-04-265-12/+12
| * riscv: add __init section marker to some functionsJisheng Zhang2021-04-264-8/+8
| * riscv: Prepare ptdump for vm layout dynamic addressesAlexandre Ghiti2021-04-261-12/+61
| * riscv: Move kernel mapping outside of linear mappingAlexandre Ghiti2021-04-2612-36/+182
| * riscv: Select HAVE_DYNAMIC_FTRACE when -fpatchable-function-entry is availableNathan Chancellor2021-04-261-1/+1
| * riscv: Workaround mcount name prior to clang-13Nathan Chancellor2021-04-262-7/+17
| * riscv: Use $(LD) instead of $(CC) to link vDSONathan Chancellor2021-04-261-8/+4
| * riscv: sifive: Apply errata "cip-1200" patchVincent Chen2021-04-264-2/+40
| * riscv: sifive: Apply errata "cip-453" patchVincent Chen2021-04-266-3/+94
| * riscv: sifive: Add SiFive alternative portsVincent Chen2021-04-267-0/+89
| * riscv: Introduce alternative mechanism to apply errata solutionVincent Chen2021-04-2614-0/+300
| * riscv: Add 3 SBI wrapper functions to get cpu manufacturer informationVincent Chen2021-04-262-0/+18
| * riscv: Cleanup KASAN_VMALLOC supportAlexandre Ghiti2021-03-291-41/+18
| * RISC-V: Don't print SBI version for all detected extensionsAnup Patel2021-03-291-3/+3
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