| Commit message (Expand) | Author | Age | Files | Lines |
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| * | RISC-V: Add PCIe I/O BAR memory mapping | Yash Shah | 2019-10-28 | 2 | -1/+13 |
| * | riscv: for C functions called only from assembly, mark with __visible | Paul Walmsley | 2019-10-28 | 5 | -8/+8 |
| * | riscv: fp: add missing __user pointer annotations | Paul Walmsley | 2019-10-28 | 1 | -2/+2 |
| * | riscv: add missing header file includes | Paul Walmsley | 2019-10-28 | 13 | -0/+17 |
| * | riscv: mark some code and data as file-static | Paul Walmsley | 2019-10-28 | 2 | -2/+2 |
| * | riscv: init: merge split string literals in preprocessor directive | Paul Walmsley | 2019-10-28 | 1 | -2/+1 |
| * | riscv: add prototypes for assembly language functions from head.S | Paul Walmsley | 2019-10-28 | 5 | -0/+29 |
| * | riscv: cleanup do_trap_break | Christoph Hellwig | 2019-10-25 | 1 | -20/+6 |
| * | riscv: cleanup <asm/bug.h> | Christoph Hellwig | 2019-10-23 | 1 | -13/+3 |
| * | riscv: Fix undefined reference to vmemmap_populate_basepages | Kefeng Wang | 2019-10-23 | 1 | -1/+1 |
| * | riscv: Fix implicit declaration of 'page_to_section' | Kefeng Wang | 2019-10-23 | 1 | -4/+1 |
| * | riscv: fix fs/proc/kcore.c compilation with sparsemem enabled | David Abdurachmanov | 2019-10-23 | 1 | -2/+0 |
| * | RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_START | Greentime Hu | 2019-10-15 | 1 | -8/+8 |
| * | riscv: tlbflush: remove confusing comment on local_flush_tlb_all() | Paul Walmsley | 2019-10-14 | 1 | -4/+0 |
| * | riscv: dts: HiFive Unleashed: add default chosen/stdout-path | Paul Walmsley | 2019-10-14 | 1 | -0/+1 |
| * | riscv: remove the switch statement in do_trap_break() | Vincent Chen | 2019-10-14 | 1 | -11/+11 |
| * | RISC-V: entry: Remove unneeded need_resched() loop | Valentin Schneider | 2019-10-09 | 1 | -2/+1 |
| * | riscv: Correct the handling of unexpected ebreak in do_trap_break() | Vincent Chen | 2019-10-07 | 1 | -3/+3 |
| * | riscv: avoid sending a SIGTRAP to a user thread trapped in WARN() | Vincent Chen | 2019-10-07 | 1 | -1/+1 |
| * | riscv: avoid kernel hangs when trapped in BUG() | Vincent Chen | 2019-10-07 | 1 | -3/+3 |
| * | riscv: Fix memblock reservation for device tree blob | Albert Ou | 2019-10-01 | 1 | -1/+11 |
| * | RISC-V: Clear load reservations while restoring hart contexts | Palmer Dabbelt | 2019-10-01 | 2 | -1/+21 |
| * | Merge tag 'riscv/for-v5.4-rc1-b' of git://git.kernel.org/pub/scm/linux/kernel... | Linus Torvalds | 2019-09-27 | 9 | -19/+73 |
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| | * | riscv: Avoid interrupts being erroneously enabled in handle_exception() | Vincent Chen | 2019-09-20 | 1 | -1/+5 |
| | * | riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes | Bin Meng | 2019-09-20 | 1 | -3/+0 |
| | * | riscv: dts: sifive: Add ethernet0 to the aliases node | Bin Meng | 2019-09-20 | 1 | -0/+1 |
| | * | RISC-V: Export kernel symbols for kvm | Atish Patra | 2019-09-20 | 2 | -0/+2 |
| | * | arch/riscv: disable excess harts before picking main boot hart | Xiang Wang | 2019-09-20 | 1 | -3/+5 |
| | * | RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig | Anup Patel | 2019-09-19 | 2 | -0/+22 |
| | * | RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=y | Greentime Hu | 2019-09-19 | 1 | -12/+12 |
| | * | riscv: dts: Add DT support for SiFive FU540 PWM driver | Yash Shah | 2019-09-19 | 2 | -0/+26 |
| * | | mm: treewide: clarify pgtable_page_{ctor,dtor}() naming | Mark Rutland | 2019-09-26 | 1 | -1/+1 |
| * | | riscv: make mmap allocation top-down by default | Alexandre Ghiti | 2019-09-24 | 1 | -0/+12 |
| * | | mm: consolidate pgtable_cache_init() and pgd_cache_init() | Mike Rapoport | 2019-09-24 | 1 | -5/+0 |
| * | | mm: remove quicklist page table caches | Nicholas Piggin | 2019-09-24 | 1 | -4/+0 |
| * | | Merge tag 'kbuild-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/masa... | Linus Torvalds | 2019-09-20 | 2 | -1/+2 |
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| | * | kbuild: add CONFIG_ASM_MODVERSIONS | Masahiro Yamada | 2019-08-22 | 1 | -0/+1 |
| | * | kbuild: rebuild modules when module linker scripts are updated | Masahiro Yamada | 2019-08-21 | 1 | -1/+1 |
| * | | Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g... | Linus Torvalds | 2019-09-16 | 24 | -110/+369 |
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| | * | | riscv: move the TLB flush logic out of line | Christoph Hellwig | 2019-09-05 | 3 | -30/+45 |
| | * | | riscv: don't use the rdtime(h) pseudo-instructions | Christoph Hellwig | 2019-09-05 | 1 | -23/+21 |
| | * | | riscv: cleanup riscv_cpuid_to_hartid_mask | Christoph Hellwig | 2019-09-05 | 4 | -8/+1 |
| | * | | riscv: optimize send_ipi_single | Christoph Hellwig | 2019-09-05 | 1 | -1/+7 |
| | * | | riscv: cleanup send_ipi_mask | Christoph Hellwig | 2019-09-05 | 1 | -9/+7 |
| | * | | riscv: refactor the IPI code | Christoph Hellwig | 2019-09-05 | 1 | -24/+31 |
| | * | | riscv: Add support for perf registers sampling | Mao Han | 2019-09-05 | 4 | -0/+89 |
| | * | | riscv: Add perf callchain support | Mao Han | 2019-09-04 | 4 | -3/+101 |
| | * | | riscv: add arch/riscv/Kbuild | Masahiro Yamada | 2019-08-30 | 2 | -1/+4 |
| | * | | RISC-V: Implement sparsemem | Logan Gunthorpe | 2019-08-30 | 5 | -0/+57 |
| | * | | riscv: Using CSR numbers to access CSRs | Bin Meng | 2019-08-30 | 6 | -21/+16 |
