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path: root/arch/x86/include/asm/perf_event.h
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* perf/amd/ibs: Add support for L3 miss filteringRavi Bangoria2022-05-111-0/+3
* Merge branch 'v5.18-rc5'Peter Zijlstra2022-05-111-0/+5
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| * perf/x86/intel: Don't extend the pseudo-encoding to GP countersKan Liang2022-04-051-0/+5
* | perf/x86/amd/core: Detect available countersSandipan Das2022-05-041-0/+17
* | perf/x86/amd: Add idle hooks for branch samplingStephane Eranian2022-04-051-0/+23
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* perf/x86/intel: Increase max number of the fixed countersKan Liang2022-02-021-1/+1
* perf/x86: Reset the dirty counter to prevent the leak for an RDPMC taskKan Liang2021-06-171-0/+1
* perf/x86/intel: Add perf core PMU support for Sapphire RapidsKan Liang2021-02-011-2/+6
* perf/x86/intel: Filter unsupported Topdown metrics eventKan Liang2021-02-011-2/+8
* x86/perf: Use static_call for x86_pmu.guest_get_msrsLike Xu2021-01-271-5/+1
* perf/x86/intel: Make anythread filter support conditionalStephane Eranian2020-11-091-1/+3
* perf/x86/amd/ibs: Support 27-bit extended Op/cycle counterKim Phillips2020-09-101-0/+1
* perf/x86/intel: Support TopDown metrics on Ice LakeKan Liang2020-08-181-0/+2
* perf/x86: Add a macro for RDPMC offset of fixed countersKan Liang2020-08-181-0/+3
* perf/x86/intel: Generic support for hardware TopDown metricsKan Liang2020-08-181-0/+47
* perf/x86/intel: Move BTS index to 47Kan Liang2020-08-181-2/+2
* perf/x86/intel: Introduce the fourth fixed counterKan Liang2020-08-181-3/+20
* perf/x86/intel: Name the global status bit in NMI handlerKan Liang2020-08-181-10/+12
* perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switchKan Liang2020-07-081-4/+0
* perf/x86/intel/lbr: Unify the stored format of LBR informationKan Liang2020-07-081-5/+1
* perf/x86: Expose CPUID enumeration bits for arch LBRKan Liang2020-07-081-0/+40
* perf/x86: Add constraint to create guest LBR event without hw counterLike Xu2020-07-021-1/+21
* perf/x86/lbr: Add interface to get LBR informationLike Xu2020-07-021-0/+12
* perf/amd/uncore: Add support for Family 19h L3 PMUKim Phillips2020-03-171-2/+13
* perf/x86: Provide stubs of KVM helpers for non-Intel CPUsSean Christopherson2020-01-131-7/+15
* perf/x86/amd/ibs: Fix sample bias for dispatched micro-opsKim Phillips2019-08-301-4/+8
* perf/x86: Make perf callchains work without CONFIG_FRAME_POINTERKairui Song2019-04-291-6/+1
* perf/x86/intel: Add Icelake supportKan Liang2019-04-161-1/+1
* perf/x86/intel: Support adaptive PEBS v4Kan Liang2019-04-161-0/+43
* perf/x86: Support outputting XMM registersKan Liang2019-04-161-0/+5
* Merge branch 'x86/cache' into perf/core, to resolve conflictsIngo Molnar2018-10-021-0/+1
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| * perf/x86: Add helper to obtain performance counter indexReinette Chatre2018-09-281-0/+1
* | perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf eventsNatarajan, Janakarajan2018-10-021-0/+8
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* License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
* perf/x86/intel/pt: Don't die on VMXONAlexander Shishkin2016-04-281-0/+4
* perf/x86/intel: Add definition for PT PMI bitStephane Eranian2016-03-081-0/+1
* x86: Add new MSRs and MSR bits used for Intel Skylake PMU supportAndi Kleen2015-08-041-0/+7
* perf/x86/amd/ibs: Update IBS MSRs and feature definitionsAravind Gopalakrishnan2014-11-121-0/+3
* perf/x86: Revamp PEBS event selectionAndi Kleen2014-08-131-0/+8
* perf/x86/intel: Add simple Haswell PMU supportAndi Kleen2013-06-191-0/+3
* perf/x86/amd: Enable northbridge performance counters on AMD family 15hJacob Shin2013-02-161-0/+9
* perf/x86/amd: Use proper naming scheme for AMD bit field definitionsJacob Shin2013-02-061-2/+2
* perf: Factor __output_copy to be usable with specific copy functionFrederic Weisbecker2012-08-101-0/+2
* perf/x86: Fix USER/KERNEL tagging of samples properlyPeter Zijlstra2012-07-311-3/+8
* perf/x86: Fix missing struct before structure nameJovi Zhang2012-07-261-1/+1
* perf/x86: Add a microcode revision check for SNB-PEBSPeter Zijlstra2012-07-051-0/+2
* perf/x86/amd: Unify AMD's generic and family 15h pmusRobert Richter2012-07-051-2/+1
* perf/x86: Rename Intel specific macrosRobert Richter2012-07-051-9/+8
* perf/x86/ibs: Fix undefined reference to `get_ibs_caps'Robert Richter2012-05-141-0/+4
* perf/x86-ibs: Take instruction pointer from ibs sampleRobert Richter2012-05-091-2/+4
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