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* Merge tag 'x86-timers-2020-03-30' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds2020-03-301-16/+112
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| * x86/tsc_msr: Make MSR derived TSC frequency more accurateHans de Goede2020-03-111-11/+86
| * x86/tsc_msr: Fix MSR_FSB_FREQ mask for Cherry Trail devicesHans de Goede2020-03-111-2/+15
| * x86/tsc_msr: Use named struct initializersHans de Goede2020-03-111-10/+18
* | x86/kernel: Convert to new CPU match macrosThomas Gleixner2020-03-241-7/+7
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* x86/cpu: Update init data for new Airmont CPU modelRahul Tanwar2019-09-061-0/+5
* x86/apic: Rename 'lapic_timer_frequency' to 'lapic_timer_period'Daniel Drake2019-05-091-2/+2
* x86/cpu: Sanitize FAM6_ATOM namingPeter Zijlstra2018-10-021-5/+5
* x86/platform/intel-mid: Remove custom TSC calibrationAndy Shevchenko2018-07-031-0/+5
* x86/tsc: Use SPDX identifier and update Intel copyrightAndy Shevchenko2018-07-031-4/+3
* x86/tsc: Convert to use x86_match_cpu() and INTEL_CPU_FAM6()Andy Shevchenko2018-07-031-41/+42
* x86/tsc: Add missing header to tsc_msr.cAndy Shevchenko2018-07-031-0/+1
* x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Atom SoCsBin Gao2016-11-181-0/+19
* x86/tsc_msr: Remove irqoff around MSR-based TSC enumerationLen Brown2016-07-111-1/+1
* x86/tsc_msr: Add Airmont reference clock valuesLen Brown2016-07-101-1/+4
* x86/tsc_msr: Correct Silvermont reference clock valuesLen Brown2016-07-101-3/+3
* x86/tsc_msr: Update comments, expand definitionsLen Brown2016-07-101-26/+10
* x86/tsc_msr: Remove debugging messagesLen Brown2016-07-101-16/+3
* x86/tsc_msr: Identify Intel-specific codeLen Brown2016-07-101-0/+3
* Revert "x86/tsc: Add missing Cherrytrail frequency to the table"Len Brown2016-07-101-3/+0
* x86/tsc: Add missing Cherrytrail frequency to the tableJeremy Compostella2016-05-121-0/+3
* x86/tsc: Read all ratio bits from MSR_PLATFORM_INFOChen Yu2016-05-061-1/+1
* x86: tsc: Add missing Baytrail frequency to the tableMika Westerberg2014-02-191-1/+1
* x86, tsc: Fallback to normal calibration if fast MSR calibration failsThomas Gleixner2014-02-191-14/+14
* x86, tsc, apic: Unbreak static (MSR) calibration when CONFIG_X86_LOCAL_APIC=nH. Peter Anvin2014-01-161-0/+2
* x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCsBin Gao2014-01-151-0/+125
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