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path: root/drivers/bus/ti-sysc.c
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* bus: ti-sysc: Fix missing reset delay handlingTony Lindgren2019-12-121-0/+4
* bus: ti-sysc: Fix missing force mstandby quirk handlingTony Lindgren2019-12-101-1/+2
* bus: ti-sysc: Adjust exception handling in sysc_child_add_named_clock()Markus Elfring2019-11-141-4/+3
* bus: ti-sysc: Add module enable quirk for audio AESSTony Lindgren2019-11-141-1/+13
* bus: ti-sysc: Use swsup quirks also for am335x musbTony Lindgren2019-10-211-0/+2
* bus: ti-sysc: Handle mstandby quirk and use it for musbTony Lindgren2019-10-211-2/+8
* Merge branch 'watchdog-fix' into omap-for-v5.5/ti-syscTony Lindgren2019-10-181-4/+14
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| * bus: ti-sysc: Fix watchdog quirk handlingTony Lindgren2019-10-181-4/+14
* | bus: ti-sysc: avoid toggling power state of module during probeTero Kristo2019-10-081-12/+18
* | bus: ti-sysc: drop the extra hardreset during initTero Kristo2019-10-081-36/+1
* | bus: ti-sysc: re-order reset and main clock controlsTero Kristo2019-10-081-4/+4
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* Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc...Linus Torvalds2019-09-301-15/+37
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| * bus: ti-sysc: Remove unpaired sysc_clkdm_deny_idle()Tony Lindgren2019-09-061-1/+0
| * bus: ti-sysc: Fix handling of invalid clocksTony Lindgren2019-09-051-4/+1
| * bus: ti-sysc: Fix clock handling for no-idle quirksTony Lindgren2019-09-051-11/+37
* | bus: ti-sysc: Detect d2d when debug is enabledTony Lindgren2019-08-261-0/+2
* | bus: ti-sysc: Add module enable quirk for SGX on omap36xxTony Lindgren2019-08-261-0/+21
* | bus: ti-sysc: Change return types of functionsNishka Dasgupta2019-08-261-16/+6
* | bus: ti-sysc: remove set but not used variable 'quirks'YueHaibing2019-08-131-2/+1
* | bus: ti-sysc: allow reset sharing across devicesTero Kristo2019-08-131-3/+9
* | bus: ti-sysc: rework the reset handlingTero Kristo2019-08-131-20/+5
* | bus: ti-sysc: re-order the clkdm control around reset handlingTero Kristo2019-08-131-4/+5
* | bus: ti-sysc: Add missing kerneldoc commentsSuman Anna2019-08-131-0/+7
* | bus: ti-sysc: Switch to SPDX license identifierSuman Anna2019-08-131-9/+1
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* bus: ti-sysc: Simplify cleanup upon failures in sysc_probe()Suman Anna2019-08-131-7/+7
* ARM: dts: Fix incorrect dcan register mapping for am3, am4 and dra7Tony Lindgren2019-07-241-1/+2
* bus: ti-sysc: Fix using configured sysc mask valueTony Lindgren2019-07-241-4/+1
* bus: ti-sysc: Fix handling of forced idleTony Lindgren2019-07-241-1/+1
* bus: ti-sysc: Add support for module specific reset quirksTony Lindgren2019-06-101-5/+124
* bus: ti-sysc: Detect uarts also on omap34xxTony Lindgren2019-05-281-1/+3
* bus: ti-sysc: Do rstctrl reset handling in two phasesTony Lindgren2019-05-281-8/+17
* bus: ti-sysc: Add support for disabling module without legacy modeTony Lindgren2019-05-281-4/+17
* bus: ti-sysc: Set ENAWAKEUP if availableTony Lindgren2019-05-281-0/+5
* bus: ti-sysc: Handle swsup idle mode quirksTony Lindgren2019-05-281-8/+17
* bus: ti-sysc: Handle clockactivity for enable and disableTony Lindgren2019-05-281-0/+7
* bus: ti-sysc: Enable interconnect target module autoidle bit on enableTony Lindgren2019-05-281-1/+12
* bus: ti-sysc: Allow QUIRK_LEGACY_IDLE even if legacy_mode is not setTony Lindgren2019-05-281-3/+0
* bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bitsTony Lindgren2019-05-281-18/+54
* bus: ti-sysc: Support 16-bit writes tooTony Lindgren2019-05-281-1/+22
* bus: ti-sysc: Add support for missing clockdomain handlingTony Lindgren2019-05-281-26/+101
* bus: ti-sysc: Handle devices with no control registersTony Lindgren2019-05-021-12/+11
* bus: ti-sysc: Add generic enable/disable functionsRoger Quadros2019-04-091-0/+129
* bus: ti-sysc: Detect DMIC for debuggingTony Lindgren2019-04-051-0/+1
* bus: ti-sysc: Handle swsup idle mode quirksTony Lindgren2019-04-051-3/+3
* bus: ti-sysc: Add quirk handling for external optional functional clockTony Lindgren2019-04-031-1/+90
* bus: ti-sysc: Add support for early quirks based on register addressTony Lindgren2019-04-031-4/+42
* bus: ti-sysc: Move rstctrl reset to happen laterTony Lindgren2019-04-031-22/+39
* bus: ti-sysc: Manage clocks for the interconnect target module in all casesTony Lindgren2019-04-031-13/+11
* bus: ti-sysc: Allocate mdata as needed and do platform data based init laterTony Lindgren2019-04-031-15/+39
* bus: ti-sysc: Enable all clocks directly during init to read revisionTony Lindgren2019-04-031-22/+28
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