| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT | Christoph Hellwig | 2023-10-26 | 1 | -1/+1 |
| * | cache: Add L2 cache management for Andes AX45MP RISC-V core | Lad Prabhakar | 2023-09-01 | 3 | -0/+227 |
 |
index : linux.git | |
| Linux kernel mainline tree | Linus Torvalds |
| summaryrefslogtreecommitdiffstats |