| Commit message (Expand) | Author | Age | Files | Lines |
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| * | clk: at91: generated: consider range when calculating best rate | Codrin Ciubotariu | 2022-05-17 | 1 | -0/+4 |
| *-. | Merge branches 'clk-starfive', 'clk-ti', 'clk-terminate' and 'clk-cleanup' in... | Stephen Boyd | 2022-03-29 | 1 | -1/+1 |
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| | | * | clk: cleanup comments | Tom Rix | 2022-03-11 | 1 | -1/+1 |
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| * | | clk: at91: clk-master: remove dead code | Claudiu Beznea | 2022-03-08 | 13 | -134/+18 |
| * | | clk: at91: sama7g5: fix parents of PDMCs' GCLK | Codrin Ciubotariu | 2022-03-08 | 1 | -4/+4 |
| * | | clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT | Tudor Ambarus | 2022-01-24 | 1 | -1/+7 |
| * | | clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT | Zixun LI | 2022-01-24 | 1 | -1/+3 |
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| * | clk: at91: sama7g5: set low limit for mck0 at 32KHz | Claudiu Beznea | 2021-10-26 | 1 | -1/+1 |
| * | clk: at91: sama7g5: remove prescaler part of master clock | Claudiu Beznea | 2021-10-26 | 1 | -10/+1 |
| * | clk: at91: clk-master: add notifier for divider | Claudiu Beznea | 2021-10-26 | 13 | -82/+186 |
| * | clk: at91: clk-sam9x60-pll: add notifier for div part of PLL | Claudiu Beznea | 2021-10-26 | 4 | -29/+95 |
| * | clk: at91: clk-master: fix prescaler logic | Claudiu Beznea | 2021-10-26 | 1 | -1/+1 |
| * | clk: at91: clk-master: mask mckr against layout->mask | Claudiu Beznea | 2021-10-26 | 1 | -2/+5 |
| * | clk: at91: clk-master: check if div or pres is zero | Claudiu Beznea | 2021-10-26 | 1 | -2/+2 |
| * | clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL | Claudiu Beznea | 2021-10-26 | 1 | -2/+2 |
| * | clk: at91: pmc: add sama7g5 to the list of available pmcs | Claudiu Beznea | 2021-10-26 | 1 | -2/+3 |
| * | clk: at91: clk-master: improve readability by using local variables | Claudiu Beznea | 2021-10-26 | 1 | -3/+3 |
| * | clk: at91: clk-master: add register definition for sama7g5's master clock | Claudiu Beznea | 2021-10-26 | 1 | -27/+23 |
| * | clk: at91: sama7g5: add securam's peripheral clock | Claudiu Beznea | 2021-10-26 | 1 | -0/+1 |
| * | clk: at91: pmc: execute suspend/resume only for backup mode | Claudiu Beznea | 2021-10-26 | 1 | -0/+39 |
| * | clk: at91: re-factor clocks suspend/resume | Claudiu Beznea | 2021-10-26 | 12 | -181/+558 |
| * | clk: at91: check pmc node status before registering syscore ops | Clément Léger | 2021-10-07 | 1 | -0/+5 |
| *-. | Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-rali... | Stephen Boyd | 2021-09-01 | 1 | -7/+7 |
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| | | * | clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings | Randy Dunlap | 2021-08-28 | 1 | -7/+7 |
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| * / | clk: at91: clk-generated: Limit the requested rate to our range | Codrin Ciubotariu | 2021-08-28 | 1 | -0/+6 |
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| * | clk: at91: Trivial typo fixes in the file sama7g5.c | Bhaskar Chowdhury | 2021-03-13 | 1 | -3/+3 |
| * | clk: at91: Fix the declaration of the clocks | Tudor Ambarus | 2021-02-09 | 9 | -28/+28 |
| * | clk: at91: sam9x60: remove atmel,osc-bypass support | Alexandre Belloni | 2020-12-19 | 1 | -5/+1 |
| * | clk: at91: sama7g5: register cpu clock | Claudiu Beznea | 2020-12-19 | 1 | -7/+6 |
| * | clk: at91: clk-master: re-factor master clock | Claudiu Beznea | 2020-12-19 | 14 | -146/+542 |
| * | clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz | Claudiu Beznea | 2020-12-19 | 1 | -14/+47 |
| * | clk: at91: sama7g5: decrease lower limit for MCK0 rate | Claudiu Beznea | 2020-12-19 | 1 | -1/+1 |
| * | clk: at91: sama7g5: remove mck0 from parent list of other clocks | Claudiu Beznea | 2020-12-19 | 1 | -29/+26 |
| * | clk: at91: clk-sam9x60-pll: allow runtime changes for pll | Claudiu Beznea | 2020-12-19 | 4 | -41/+197 |
| * | clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics | Eugen Hristev | 2020-12-19 | 1 | -2/+2 |
| * | clk: at91: clk-master: add 5th divisor for mck master | Eugen Hristev | 2020-12-19 | 2 | -2/+2 |
| * | clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT | Eugen Hristev | 2020-12-19 | 1 | -2/+4 |
| * | dt-bindings: clock: at91: add sama7g5 pll defines | Eugen Hristev | 2020-12-19 | 1 | -3/+3 |
| * | clk: at91: sama7g5: fix compilation error | Claudiu Beznea | 2020-12-19 | 1 | -2/+4 |
| *-. | Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom... | Stephen Boyd | 2020-10-20 | 4 | -8/+12 |
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| | | * | clk: at91: sam9x60: support only two programmable clocks | Claudiu Beznea | 2020-10-14 | 1 | -1/+1 |
| | | * | clk: at91: clk-sam9x60-pll: remove unused variable | Claudiu Beznea | 2020-10-13 | 1 | -2/+1 |
| | | * | clk: at91: clk-main: update key before writing AT91_CKGR_MOR | Claudiu Beznea | 2020-10-13 | 1 | -3/+8 |
| | | * | clk: at91: remove the checking of parent_name | Claudiu Beznea | 2020-10-13 | 1 | -2/+2 |
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| * / | clk: at91: drop unused at91sam9g45_pcr_layout | Krzysztof Kozlowski | 2020-09-22 | 1 | -7/+0 |
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| * | clk: at91: sama7g5: add clock support for sama7g5 | Claudiu Beznea | 2020-07-24 | 2 | -0/+1060 |
| * | clk: at91: clk-utmi: add utmi support for sama7g5 | Claudiu Beznea | 2020-07-24 | 2 | -5/+102 |
| * | clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs | Claudiu Beznea | 2020-07-24 | 3 | -186/+433 |
| * | clk: at91: clk-programmable: add mux_table option | Claudiu Beznea | 2020-07-24 | 13 | -17/+38 |
| * | clk: at91: clk-peripheral: add support for changeable parent rate | Claudiu Beznea | 2020-07-24 | 9 | -16/+119 |
