| Commit message (Expand) | Author | Age | Files | Lines |
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| * | clk: Add Ingenic JZ4755 CGU driver | Siarhei Volkau | 2022-11-01 | 3 | -0/+357 |
| * | clk: ingenic: Minor cosmetic fixups for X1000 | Aidan MacDonald | 2022-10-27 | 1 | -25/+24 |
| * | clk: ingenic: Add X1000 audio clocks | Aidan MacDonald | 2022-10-27 | 1 | -0/+70 |
| * | clk: ingenic: Add .set_rate_hook() for PLL clocks | Aidan MacDonald | 2022-10-27 | 2 | -0/+7 |
| * | clk: ingenic: Make PLL clock enable_bit and stable_bit optional | Aidan MacDonald | 2022-10-27 | 2 | -5/+19 |
| * | clk: ingenic: Make PLL clock "od" field optional | Aidan MacDonald | 2022-10-27 | 2 | -9/+19 |
| * | clk: ingenic-tcu: Properly enable registers before accessing timers | Aidan MacDonald | 2022-08-31 | 1 | -10/+5 |
| * | clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs | Aidan MacDonald | 2022-05-18 | 1 | -10/+25 |
| * | clk: ingenic: Mark critical clocks in Ingenic SoCs | Aidan MacDonald | 2022-05-18 | 7 | -0/+76 |
| * | clk: ingenic: Allow specifying common clock flags | Aidan MacDonald | 2022-05-18 | 2 | -1/+4 |
| * | clk: jz4725b: fix mmc0 clock gating | Siarhei Volkau | 2022-02-17 | 1 | -2/+1 |
| * | clk: ingenic: Add MDMA and BDMA clocks | Paul Cercueil | 2022-01-06 | 2 | -0/+15 |
| * | Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux... | Linus Torvalds | 2021-11-14 | 7 | -7/+7 |
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| | * | dt-bindings: Rename Ingenic CGU headers to ingenic,*.h | Paul Cercueil | 2021-11-11 | 7 | -7/+7 |
| * | | clk: ingenic: Fix bugs with divided dividers | Paul Cercueil | 2021-11-02 | 1 | -3/+3 |
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| * | clk: ingenic: Add support for the JZ4760 | Paul Cercueil | 2021-06-27 | 4 | -0/+441 |
| * | clk: ingenic: Support overriding PLLs M/N/OD calc algorithm | Paul Cercueil | 2021-06-27 | 2 | -13/+30 |
| * | clk: ingenic: Remove pll_info.no_bypass_bit | Paul Cercueil | 2021-06-27 | 3 | -8/+6 |
| * | clk: ingenic: Read bypass register only when there is one | Paul Cercueil | 2021-06-27 | 1 | -8/+11 |
| * | clk: Support bypassing dividers | Paul Cercueil | 2021-06-27 | 5 | -29/+42 |
| * | clk: ingenic: Fix divider calculation with div tables | Paul Cercueil | 2020-12-19 | 1 | -4/+10 |
| * | clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate | Paul Cercueil | 2020-10-13 | 1 | -0/+2 |
| * | clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT | Paul Cercueil | 2020-10-13 | 1 | -7/+7 |
| * | clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL | Paul Cercueil | 2020-10-13 | 1 | -2/+7 |
| * | clk: ingenic: Use readl_poll_timeout instead of custom loop | Paul Cercueil | 2020-10-13 | 1 | -26/+29 |
| * | clk: ingenic: Use to_clk_info() macro for all clocks | Paul Cercueil | 2020-10-13 | 1 | -39/+15 |
| * | clk: X1000: Add support for calculat REFCLK of USB PHY. | 周琰杰 (Zhou Yanjie) | 2020-07-27 | 1 | -1/+83 |
| * | clk: JZ4780: Reformat the code to align it. | 周琰杰 (Zhou Yanjie) | 2020-07-27 | 1 | -45/+45 |
| * | clk: JZ4780: Add functions for enable and disable USB PHY. | 周琰杰 (Zhou Yanjie) | 2020-07-27 | 1 | -30/+35 |
| * | clk: Ingenic: Add RTC related clocks for Ingenic SoCs. | 周琰杰 (Zhou Yanjie) | 2020-07-27 | 3 | -0/+38 |
| * | clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused | Stephen Boyd | 2020-05-28 | 1 | -1/+1 |
| * | clk: X1000: Add FIXDIV for SSI clock of X1000. | 周琰杰 (Zhou Yanjie) | 2020-05-28 | 1 | -6/+111 |
| * | clk: Ingenic: Add CGU driver for X1830. | 周琰杰 (Zhou Yanjie) | 2020-05-28 | 3 | -0/+459 |
| * | clk: Ingenic: Adjust cgu code to make it compatible with X1830. | 周琰杰 (Zhou Yanjie) | 2020-05-28 | 7 | -4/+41 |
| * | clk: Ingenic: Remove unnecessary spinlock when reading registers. | 周琰杰 (Zhou Yanjie) | 2020-05-28 | 1 | -11/+1 |
| * | clk: ingenic/TCU: Fix round_rate returning error | Paul Cercueil | 2020-03-20 | 1 | -1/+1 |
| * | clk: ingenic/jz4770: Exit with error if CGU init failed | Paul Cercueil | 2020-03-20 | 1 | -1/+3 |
| * | clk: JZ4780: Add function for enable the second core. | 周琰杰 (Zhou Yanjie) | 2020-03-20 | 1 | -5/+50 |
| * | clk: Ingenic: Add support for TCU of X1000. | 周琰杰 (Zhou Yanjie) | 2020-03-20 | 1 | -0/+8 |
| *-. | Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ... | Stephen Boyd | 2019-11-27 | 3 | -1/+286 |
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| | * | | clk: ingenic: Allow drivers to be built with COMPILE_TEST | Stephen Boyd | 2019-11-22 | 1 | -1/+1 |
| | * | | clk: Ingenic: Add CGU driver for X1000. | Zhou Yanjie | 2019-11-13 | 3 | -0/+285 |
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| * / | drivers/clk: convert VL struct to struct_size | Stephen Kitt | 2019-11-08 | 1 | -2/+1 |
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| * | Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux | Linus Torvalds | 2019-09-22 | 4 | -1/+490 |
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| | * | clk: jz4740: Add TCU clock | Paul Cercueil | 2019-08-08 | 1 | -0/+6 |
| | * | clk: ingenic: Add driver for the TCU clocks | Paul Cercueil | 2019-08-08 | 3 | -1/+484 |
| * | | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro | Paul Cercueil | 2019-08-12 | 4 | -4/+4 |
| * | | clk: ingenic/jz4740: Fix "pll half" divider not read/written properly | Paul Cercueil | 2019-08-07 | 1 | -1/+8 |
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| * | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2019-07-17 | 9 | -128/+192 |
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| | * | clk: ingenic: Remove unused functions | Paul Cercueil | 2019-06-25 | 1 | -73/+0 |
