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path: root/drivers/clk/ingenic
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* clk: ingenic-tcu: Properly enable registers before accessing timersAidan MacDonald2022-08-311-10/+5
* clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCsAidan MacDonald2022-05-181-10/+25
* clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald2022-05-187-0/+76
* clk: ingenic: Allow specifying common clock flagsAidan MacDonald2022-05-182-1/+4
* clk: jz4725b: fix mmc0 clock gatingSiarhei Volkau2022-02-171-2/+1
* clk: ingenic: Add MDMA and BDMA clocksPaul Cercueil2022-01-062-0/+15
* Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux...Linus Torvalds2021-11-147-7/+7
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| * dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil2021-11-117-7/+7
* | clk: ingenic: Fix bugs with divided dividersPaul Cercueil2021-11-021-3/+3
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* clk: ingenic: Add support for the JZ4760Paul Cercueil2021-06-274-0/+441
* clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2021-06-272-13/+30
* clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil2021-06-273-8/+6
* clk: ingenic: Read bypass register only when there is onePaul Cercueil2021-06-271-8/+11
* clk: Support bypassing dividersPaul Cercueil2021-06-275-29/+42
* clk: ingenic: Fix divider calculation with div tablesPaul Cercueil2020-12-191-4/+10
* clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil2020-10-131-0/+2
* clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil2020-10-131-7/+7
* clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil2020-10-131-2/+7
* clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil2020-10-131-26/+29
* clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil2020-10-131-39/+15
* clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)2020-07-271-1/+83
* clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)2020-07-271-45/+45
* clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)2020-07-271-30/+35
* clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)2020-07-273-0/+38
* clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd2020-05-281-1/+1
* clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)2020-05-281-6/+111
* clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)2020-05-283-0/+459
* clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)2020-05-287-4/+41
* clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)2020-05-281-11/+1
* clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil2020-03-201-1/+1
* clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil2020-03-201-1/+3
* clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)2020-03-201-5/+50
* clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)2020-03-201-0/+8
*-. Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd2019-11-273-1/+286
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| * | clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd2019-11-221-1/+1
| * | clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie2019-11-133-0/+285
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* / drivers/clk: convert VL struct to struct_sizeStephen Kitt2019-11-081-2/+1
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* Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2019-09-224-1/+490
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| * clk: jz4740: Add TCU clockPaul Cercueil2019-08-081-0/+6
| * clk: ingenic: Add driver for the TCU clocksPaul Cercueil2019-08-083-1/+484
* | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil2019-08-124-4/+4
* | clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil2019-08-071-1/+8
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-179-128/+192
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| * clk: ingenic: Remove unused functionsPaul Cercueil2019-06-251-73/+0
| * clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil2019-06-257-32/+69
| * clk: ingenic: Add missing header in cgu.hPaul Cercueil2019-06-251-0/+1
| * clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil2019-06-071-1/+8
| * clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-5/+24
| * clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-6/+28
| * clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-5/+24
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