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path: root/drivers/clk/mediatek/Kconfig
Commit message (Expand)AuthorAgeFilesLines
* clk: mediatek: Add drivers for MT6735 syscon clock and reset controllersYassine Oudjana14 days1-0/+28
* clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset driversYassine Oudjana2024-10-171-0/+9
* clk: mediatek: drop two dead config optionsLukas Bulwahn2024-10-091-15/+0
* clk: mediatek: add drivers for MT7988 SoCSam Shih2024-01-031-0/+9
* clk: mediatek: Enable all MT8192 clocks by defaultChen-Yu Tsai2023-05-101-0/+12
* clk: mediatek: Add MT8188 adsp clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 imp i2c wrapper clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 wpesys clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 vppsys0 clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 vencsys clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 vdosys0 clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 vdecsys clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 mfgcfg clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 ipesys clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 imgsys clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 camsys clock supportGarmin.Chang2023-03-311-0/+7
* clk: mediatek: Add MT8188 apmixedsys clock supportGarmin.Chang2023-03-311-0/+9
* clk: mediatek: mt81xx: Ensure fhctl code is availableArnd Bergmann2023-03-201-0/+3
* clk: mediatek: Ensure fhctl code is available for COMMON_CLK_MT6795Stephen Boyd2023-03-171-0/+1
* clk: mediatek: mt8135: Convert to simple probe and enable module buildAngeloGioacchino Del Regno2023-03-131-1/+1
* clk: mediatek: Kconfig: Allow module build for core mt8192 clocksAngeloGioacchino Del Regno2023-03-131-1/+1
* clk: mediatek: Split configuration options for MT8186 clock driversAngeloGioacchino Del Regno2023-03-131-1/+78
* clk: mediatek: Allow building most MT6797 clock drivers as modulesAngeloGioacchino Del Regno2023-03-131-4/+4
* clk: mediatek: Allow building most MT6765 clock drivers as modulesAngeloGioacchino Del Regno2023-03-131-13/+13
* clk: mediatek: Allow all MT8183 clocks to be built as modulesAngeloGioacchino Del Regno2023-03-131-12/+12
* clk: mediatek: Allow all MT8167 clocks to be built as modulesAngeloGioacchino Del Regno2023-03-131-8/+8
* clk: mediatek: Allow MT7622 clocks to be built as modulesAngeloGioacchino Del Regno2023-03-131-4/+4
* clk: mediatek: Allow building MT8192 non-critical clocks as modulesAngeloGioacchino Del Regno2023-03-131-12/+12
* clk: mediatek: Split MT8195 clock drivers and allow module buildAngeloGioacchino Del Regno2023-03-131-0/+100
* clk: mediatek: mt2712: Change Kconfig options to allow module buildAngeloGioacchino Del Regno2023-03-131-8/+8
* clk: mediatek: mt8516: Allow building clock drivers as modulesAngeloGioacchino Del Regno2023-03-131-2/+2
* clk: mediatek: add MT7981 clock supportDaniel Golle2023-01-301-0/+17
* clk: mediatek: mt8173: Break down clock drivers and allow module buildAngeloGioacchino Del Regno2023-01-301-5/+27
* clk: mediatek: Change PLL register API for MT8186Johnson Wang2022-11-291-0/+1
* clk: mediatek: Add new clock driver to handle FHCTL hardwareJohnson Wang2022-11-291-0/+7
* clk: mediatek: add driver for MT8365 SoCFabien Parent2022-09-301-0/+50
* clk: mediatek: Add MediaTek Helio X10 MT6795 clock driversAngeloGioacchino Del Regno2022-09-261-0/+37
* clk: mediatek: Add MT8186 mcusys clock supportChun-Jie Chen2022-04-251-0/+8
* clk: mediatek: add mt7986 clock supportSam Shih2022-01-061-0/+17
* clk: mediatek: support COMMON_CLK_MT6779 module buildMiles Chen2021-09-141-9/+9
* clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen2021-09-141-1/+1
* clk: mediatek: Add MT8195 apmixedsys clock supportChun-Jie Chen2021-09-141-0/+8
* clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167Miles Chen2021-07-271-15/+10
* clk: mediatek: Add MT8192 vencsys clock supportChun-Jie Chen2021-07-271-0/+6
* clk: mediatek: Add MT8192 vdecsys clock supportChun-Jie Chen2021-07-271-0/+6
* clk: mediatek: Add MT8192 scp adsp clock supportChun-Jie Chen2021-07-271-0/+6
* clk: mediatek: Add MT8192 msdc clock supportChun-Jie Chen2021-07-271-0/+6
* clk: mediatek: Add MT8192 mmsys clock supportChun-Jie Chen2021-07-271-0/+6
* clk: mediatek: Add MT8192 mfgcfg clock supportChun-Jie Chen2021-07-271-0/+6
* clk: mediatek: Add MT8192 mdpsys clock supportChun-Jie Chen2021-07-271-0/+6
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 09:21:24 +0000