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path:
root
/
drivers
/
clk
/
mediatek
/
clk-pll.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
Sam Shih
2024-01-03
1
-2
/
+3
*
clk: mediatek: fix double free in mtk_clk_register_pllfh()
Dan Carpenter
2023-10-24
1
-3
/
+3
*
clk: mediatek: Export PLL operations symbols
Johnson Wang
2022-11-29
1
-50
/
+34
*
clk: mediatek: Switch to clk_hw provider APIs
Chen-Yu Tsai
2022-05-19
1
-17
/
+18
*
clk: mediatek: Replace 'struct clk' with 'struct clk_hw'
Chen-Yu Tsai
2022-05-19
1
-12
/
+11
*
clk: mediatek: use en_mask as a pure div_en_mask
Chun-Jie Chen
2022-05-18
1
-8
/
+4
*
clk: mediatek: Warn if clk IDs are duplicated
Chen-Yu Tsai
2022-02-17
1
-0
/
+6
*
clk: mediatek: pll: Implement error handling in register API
Chen-Yu Tsai
2022-02-17
1
-4
/
+19
*
clk: mediatek: pll: Clean up included headers
Chen-Yu Tsai
2022-02-17
1
-5
/
+7
*
clk: mediatek: pll: Implement unregister API
Chen-Yu Tsai
2022-02-17
1
-0
/
+55
*
clk: mediatek: pll: Split definitions into separate header file
Chen-Yu Tsai
2022-02-17
1
-0
/
+1
*
clk: mediatek: Use %pe to print errors
Chen-Yu Tsai
2022-02-17
1
-2
/
+1
*
clk: mediatek: support COMMON_CLK_MEDIATEK module build
Miles Chen
2021-09-14
1
-0
/
+4
*
clk: mediatek: Fix corner case of tuner_en_reg
Chun-Jie Chen
2021-09-14
1
-1
/
+1
*
clk: mediatek: Add configurable enable control to mtk_pll_data
Chun-Jie Chen
2021-07-27
1
-5
/
+10
*
clk: mediatek: Fix asymmetrical PLL enable and disable control
Chun-Jie Chen
2021-07-27
1
-4
/
+16
*
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Thomas Gleixner
2019-05-30
1
-9
/
+1
*
clk: mediatek: Allow changing PLL rate when it is off
James Liao
2019-04-11
1
-11
/
+2
*
clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
Weiyi Lu
2019-04-11
1
-6
/
+11
*
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
Owen Chen
2019-04-11
1
-4
/
+11
*
clk: mediatek: Disable tuner_en before change PLL rate
Owen Chen
2019-04-11
1
-14
/
+34
*
clk: mediatek: add the option for determining PLL source clock
Chen Zhong
2017-11-02
1
-1
/
+4
*
clk: mediatek: Add MT2712 clock support
weiyi.lu@mediatek.com
2017-11-02
1
-2
/
+11
*
clk: mediatek: Add MT2701 clock support
Shunli Wang
2016-11-08
1
-0
/
+1
*
clk: mediatek: remove __init from clk registration functions
James Liao
2016-08-18
1
-1
/
+1
*
clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
James Liao
2015-10-01
1
-6
/
+1
*
clk: mediatek: Add MT8173 MMPLL change rate support
James Liao
2015-07-28
1
-3
/
+15
*
clk: mediatek: Fix calculation of PLL rate settings
James Liao
2015-07-28
1
-2
/
+2
*
clk: mediatek: Fix PLL registers setting flow
James Liao
2015-07-28
1
-9
/
+12
*
clk: mediatek: Initialize clk_init_data
Ricky Liang
2015-05-19
1
-1
/
+1
*
clk: mediatek: Add initial common clock support for Mediatek SoCs.
James Liao
2015-05-05
1
-0
/
+332