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path: root/drivers/clk/meson
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* clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel2021-02-092-4/+0
* clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl2021-01-041-40/+5
* clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl2021-01-041-2/+3
* clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl2021-01-041-1/+2
* clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl2021-01-041-1/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-12-2111-61/+1004
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| * clk: meson: g12a: add MIPI DSI Host Pixel ClockNeil Armstrong2020-11-262-1/+76
| * clk: meson: enable building as modulesKevin Hilman2020-11-239-9/+34
| * clk: meson: Kconfig: fix dependency for G12AKevin Hilman2020-11-231-0/+1
| * clk: meson: axg: add MIPI DSI Host clockNeil Armstrong2020-11-232-1/+69
| * clk: meson: axg: add Video ClocksNeil Armstrong2020-11-232-1/+773
| * clk: meson: g12: use devm variant to register notifiersJerome Brunet2020-11-141-14/+20
| * clk: meson: g12: drop use of __clk_lookup()Jerome Brunet2020-11-141-36/+32
* | clk: define to_clk_regmap() as inline functionArnd Bergmann2020-10-281-1/+4
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*-. Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ...Stephen Boyd2020-10-201-1/+1
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| * | clk: meson: use semicolons rather than commas to separate statementsJulia Lawall2020-10-131-1/+1
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* | clk: meson: make shipped controller configurableJerome Brunet2020-09-101-9/+17
* | clk: meson: g12a: mark fclk_div2 as criticalStefan Agner2020-08-291-0/+11
* | clk: meson: axg-audio: fix g12a tdmout sclk inverterJerome Brunet2020-08-171-25/+60
* | clk: meson: axg-audio: separate axg and g12a regmap tablesJerome Brunet2020-08-171-8/+127
* | clk: meson: add sclk-ws driverJerome Brunet2020-08-172-0/+62
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* Merge branch 'clk-amlogic' into clk-nextStephen Boyd2020-07-214-19/+178
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| * clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl2020-07-092-6/+27
| * clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl2020-07-092-6/+27
| * clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2Martin Blumenstingl2020-06-241-7/+0
| * clk: meson: g12a: Add support for NNA CLK source clocksDmitry Shmidt2020-06-192-1/+125
* | Replace HTTP links with HTTPS ones: Common CLK frameworkAlexander A. Klimov2020-07-101-1/+1
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* clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl2020-05-022-0/+13
* clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl2020-04-291-3/+11
* clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl2020-04-291-5/+5
* clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl2020-04-291-23/+56
* clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl2020-04-291-1/+1
* clk: meson: g12a: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl2020-04-161-8/+22
* clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl2020-04-161-18/+22
* clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl2020-04-141-3/+3
* clk: meson8b: export the HDMI system clockMartin Blumenstingl2020-04-141-1/+0
* clk: meson: meson8b: set audio output clock hierarchyMartin Blumenstingl2020-02-211-8/+13
* clk: meson: g12a: add support for the SPICC SCLK Source clocksNeil Armstrong2020-02-192-1/+134
* clk: meson: gxbb: set audio output clock hierarchyJerome Brunet2020-02-131-8/+10
* clk: meson: gxbb: add the gxl internal dac gateJerome Brunet2020-02-132-1/+4
*-. Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlo...Stephen Boyd2020-01-315-56/+229
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| | * clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl2020-01-071-4/+7
| | * Merge branch 'v5.5/fixes' into v5.6/driversJerome Brunet2019-12-162-0/+10
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| | | * clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel2019-12-161-0/+9
| | | * clk: meson: g12a: fix missing uart2 in regmap tableJerome Brunet2019-12-161-0/+1
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| | * clk: meson: meson8b: use of_clk_hw_register to register the clocksMartin Blumenstingl2019-12-111-1/+1
| | * clk: meson: meson8b: don't register the XTAL clock when provided via OFMartin Blumenstingl2019-12-111-3/+9
| | * clk: meson: meson8b: change references to the XTAL clock to use [fw_]nameMartin Blumenstingl2019-12-111-34/+44
| | * clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifierMartin Blumenstingl2019-12-111-13/+8
| | * clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controllerMartin Blumenstingl2019-12-112-1/+150
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