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path: root/drivers/clk/meson
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* clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()Uwe Kleine-König2022-06-151-32/+4
* clk: cleanup commentsTom Rix2022-03-111-1/+1
* clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl2021-11-301-3/+41
* clk: meson: meson8b: Make the video clock trees mutableMartin Blumenstingl2021-09-231-38/+38
* clk: meson: meson8b: Initialize the HDMI PLL registersMartin Blumenstingl2021-09-232-5/+48
* clk: meson: meson8b: Add the HDMI PLL M/N parametersMartin Blumenstingl2021-09-231-0/+22
* clk: meson: meson8b: Add the vid_pll_lvds_en gate clockMartin Blumenstingl2021-09-232-2/+24
* clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_selMartin Blumenstingl2021-09-231-2/+2
* clk: meson: meson8b: Export the video clocksMartin Blumenstingl2021-09-231-11/+1
* clk: meson: regmap: switch to determine_rate for the dividersMartin Blumenstingl2021-06-301-10/+9
* clk: meson: g12a: Add missing NNA source clocks for g12bNick Xie2021-06-091-0/+6
* clk: meson: axg-audio: improve deferral handlingJerome Brunet2021-05-241-3/+2
* clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet2021-05-201-1/+1
* clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl2021-05-191-11/+15
* clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel2021-02-092-4/+0
* clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl2021-01-041-40/+5
* clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl2021-01-041-2/+3
* clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl2021-01-041-1/+2
* clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl2021-01-041-1/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-12-2111-61/+1004
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| * clk: meson: g12a: add MIPI DSI Host Pixel ClockNeil Armstrong2020-11-262-1/+76
| * clk: meson: enable building as modulesKevin Hilman2020-11-239-9/+34
| * clk: meson: Kconfig: fix dependency for G12AKevin Hilman2020-11-231-0/+1
| * clk: meson: axg: add MIPI DSI Host clockNeil Armstrong2020-11-232-1/+69
| * clk: meson: axg: add Video ClocksNeil Armstrong2020-11-232-1/+773
| * clk: meson: g12: use devm variant to register notifiersJerome Brunet2020-11-141-14/+20
| * clk: meson: g12: drop use of __clk_lookup()Jerome Brunet2020-11-141-36/+32
* | clk: define to_clk_regmap() as inline functionArnd Bergmann2020-10-281-1/+4
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*-. Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ...Stephen Boyd2020-10-201-1/+1
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| * | clk: meson: use semicolons rather than commas to separate statementsJulia Lawall2020-10-131-1/+1
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* | clk: meson: make shipped controller configurableJerome Brunet2020-09-101-9/+17
* | clk: meson: g12a: mark fclk_div2 as criticalStefan Agner2020-08-291-0/+11
* | clk: meson: axg-audio: fix g12a tdmout sclk inverterJerome Brunet2020-08-171-25/+60
* | clk: meson: axg-audio: separate axg and g12a regmap tablesJerome Brunet2020-08-171-8/+127
* | clk: meson: add sclk-ws driverJerome Brunet2020-08-172-0/+62
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* Merge branch 'clk-amlogic' into clk-nextStephen Boyd2020-07-214-19/+178
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| * clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl2020-07-092-6/+27
| * clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl2020-07-092-6/+27
| * clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2Martin Blumenstingl2020-06-241-7/+0
| * clk: meson: g12a: Add support for NNA CLK source clocksDmitry Shmidt2020-06-192-1/+125
* | Replace HTTP links with HTTPS ones: Common CLK frameworkAlexander A. Klimov2020-07-101-1/+1
|/
* clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl2020-05-022-0/+13
* clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl2020-04-291-3/+11
* clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl2020-04-291-5/+5
* clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl2020-04-291-23/+56
* clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl2020-04-291-1/+1
* clk: meson: g12a: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl2020-04-161-8/+22
* clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl2020-04-161-18/+22
* clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl2020-04-141-3/+3
* clk: meson8b: export the HDMI system clockMartin Blumenstingl2020-04-141-1/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 22:33:36 +0000