| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) | Lad Prabhakar | 2020-09-04 | 1 | -1/+1 |
| * | clk: renesas: Convert to SPDX identifiers | Kuninori Morimoto | 2018-09-28 | 1 | -4/+1 |
| * | clk: renesas: r8a7745: Fix LB clock divider | Geert Uytterhoeven | 2018-04-16 | 1 | -1/+1 |
| * | clk: renesas: r8a7745: Add rwdt clock | Fabrizio Castro | 2018-02-20 | 1 | -0/+2 |
| * | clk: renesas: cpg-mssr: Add du1 clock to R8A7745 | Fabrizio Castro | 2017-10-20 | 1 | -0/+1 |
| * | clk: renesas: r8a7745: Remove PLL configs for MD19=0 | Geert Uytterhoeven | 2017-05-15 | 1 | -11/+2 |
| * | clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks | Geert Uytterhoeven | 2017-05-15 | 1 | -4/+0 |
| * | clk: renesas: cpg-mssr: Add R8A7745 support | Sergei Shtylyov | 2016-11-10 | 1 | -0/+259 |
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