Commit message (Expand) | Author | Age | Files | Lines | |
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* | clk: renesas: r8a77995: Simplify PLL3 multiplier/divider | Geert Uytterhoeven | 2018-12-04 | 1 | -2/+2 |
* | clk: renesas: r8a77995: Add missing CPEX clock | Geert Uytterhoeven | 2018-12-04 | 1 | -1/+2 |
* | clk: renesas: r8a77995: Remove non-existent SSP clocks | Geert Uytterhoeven | 2018-12-04 | 1 | -1/+0 |
* | clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks | Geert Uytterhoeven | 2018-12-04 | 1 | -3/+0 |
* | clk: renesas: r8a77995: Correct parent clock of DU | Geert Uytterhoeven | 2018-12-04 | 1 | -2/+2 |
* | Merge branch 'clk-renesas' into clk-next | Stephen Boyd | 2018-10-18 | 1 | -2/+10 |
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| * | clk: renesas: r8a77995: Correct RCLK handling | Geert Uytterhoeven | 2018-08-27 | 1 | -2/+10 |
* | | clk: renesas: use SPDX identifier for Renesas drivers | Wolfram Sang | 2018-08-30 | 1 | -4/+1 |
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* | clk: renesas: r8a77995: Correct parent clock of INTC-AP | Geert Uytterhoeven | 2017-10-16 | 1 | -1/+1 |
* | clk: renesas: cpg-mssr: Add R8A77995 support | Geert Uytterhoeven | 2017-08-16 | 1 | -0/+236 |