| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | clk: renesas: r8a779f0: Fix Ethernet Switch clocks | Geert Uytterhoeven | 2022-11-16 | 1 | -2/+2 |
| * | clk: renesas: r8a779g0: Add Z0 clock support | Geert Uytterhoeven | 2022-11-15 | 1 | -0/+1 |
| * | clk: renesas: r8a779g0: Add CMT clocks | Wolfram Sang | 2022-11-08 | 1 | -0/+4 |
| * | clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks | Wolfram Sang | 2022-11-08 | 1 | -0/+6 |
| * | clk: renesas: r8a779f0: Fix SCIF parent clocks | Wolfram Sang | 2022-11-08 | 1 | -4/+4 |
| * | clk: renesas: r8a779f0: Fix HSCIF parent clocks | Wolfram Sang | 2022-11-08 | 1 | -4/+4 |
| * | clk: renesas: r9a06g032: Repair grave increment error | Marek Vasut | 2022-11-01 | 1 | -2/+1 |
| * | clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM | Lad Prabhakar | 2022-10-28 | 2 | -15/+28 |
| * | clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc | Lad Prabhakar | 2022-10-26 | 1 | -1/+1 |
| * | clk: renesas: r8a779a0: Fix SD0H clock name | Wolfram Sang | 2022-10-26 | 1 | -1/+1 |
| * | clk: renesas: r8a779g0: Add RPC-IF clock | Geert Uytterhoeven | 2022-10-26 | 1 | -1/+2 |
| * | clk: renesas: r8a779g0: Add SDHI clocks | Geert Uytterhoeven | 2022-10-26 | 1 | -1/+3 |
| * | clk: renesas: r8a779f0: Add SASYNCPER internal clock | Geert Uytterhoeven | 2022-10-26 | 1 | -3/+5 |
| * | clk: renesas: r8a779f0: Fix SD0H clock name | Geert Uytterhoeven | 2022-10-26 | 1 | -1/+1 |
| * | clk: renesas: r9a07g043: Drop WDT2 clock and reset entry | Lad Prabhakar | 2022-10-26 | 1 | -5/+0 |
| * | clk: renesas: r9a07g044: Drop WDT2 clock and reset entry | Lad Prabhakar | 2022-10-26 | 1 | -6/+1 |
| * | clk: renesas: r8a779g0: Add TPU clock | Geert Uytterhoeven | 2022-10-26 | 1 | -0/+1 |
| * | clk: renesas: r8a779g0: Add PWM clock | Geert Uytterhoeven | 2022-10-26 | 1 | -0/+1 |
| * | clk: renesas: r8a779g0: Add SCIF clocks | Geert Uytterhoeven | 2022-10-26 | 1 | -0/+4 |
| * | Merge tag 'renesas-clk-fixes-for-v6.1-tag1' | Geert Uytterhoeven | 2022-10-26 | 1 | -4/+9 |
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| | * | clk: renesas: r8a779g0: Fix HSCIF parent clocks | Geert Uytterhoeven | 2022-10-26 | 1 | -4/+4 |
| | * | clk: renesas: r8a779g0: Add SASYNCPER clocks | Geert Uytterhoeven | 2022-10-18 | 1 | -0/+5 |
| * | | clk: renesas: r9a07g044: Add MTU3a clock and reset entry | Biju Das | 2022-10-17 | 1 | -1/+4 |
| * | | clk: renesas: r8a779g0: Add INTC-EX clock | Geert Uytterhoeven | 2022-10-17 | 1 | -0/+1 |
| * | | clk: renesas: r8a779g0: Add MSIOF clocks | Geert Uytterhoeven | 2022-10-17 | 1 | -0/+6 |
| * | | clk: renesas: r8a779g0: Add SYS-DMAC clocks | Geert Uytterhoeven | 2022-10-17 | 1 | -0/+2 |
| * | | clk: renesas: r8a779f0: Add Ethernet Switch clocks | Yoshihiro Shimoda | 2022-10-17 | 1 | -0/+2 |
| * | | clk: renesas: rzg2l: Fix typo in function name | Lad Prabhakar | 2022-10-17 | 1 | -3/+3 |
| * | | clk: renesas: rzg2l: Support sd clk mux round operation | Biju Das | 2022-10-17 | 1 | -1/+1 |
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| * | clk: renesas: r8a779g0: Add EtherAVB clocks | Geert Uytterhoeven | 2022-09-18 | 1 | -0/+3 |
| * | clk: renesas: r8a779g0: Add PFC/GPIO clocks | Geert Uytterhoeven | 2022-09-18 | 1 | -0/+4 |
| * | clk: renesas: r8a779g0: Add I2C clocks | Geert Uytterhoeven | 2022-09-18 | 1 | -0/+6 |
| * | clk: renesas: r8a779g0: Add watchdog clock | Geert Uytterhoeven | 2022-09-18 | 1 | -0/+1 |
| * | clk: renesas: r8a779f0: Add MSIOF clocks | Wolfram Sang | 2022-08-29 | 1 | -0/+4 |
| * | clk: renesas: r9a09g011: Add IIC clock and reset entries | Phil Edworthy | 2022-08-29 | 1 | -0/+4 |
| * | clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info | Biju Das | 2022-08-22 | 1 | -0/+2 |
| * | clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks | Wolfram Sang | 2022-08-22 | 1 | -0/+10 |
| * | clk: renesas: r8a779f0: Add CMT clocks | Wolfram Sang | 2022-08-15 | 1 | -0/+4 |
| * | clk: renesas: r8a779f0: Add SDH0 clock | Wolfram Sang | 2022-08-15 | 1 | -1/+2 |
| * | clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config | Andi Kleen | 2022-07-05 | 1 | -1/+1 |
| * | clk: renesas: r9a07g043: Add support for RZ/Five SoC | Lad Prabhakar | 2022-07-05 | 1 | -0/+32 |
| * | clk: renesas: r8a779f0: Add HSCIF clocks | Wolfram Sang | 2022-06-17 | 1 | -0/+4 |
| * | clk: renesas: r8a779f0: Add PCIe clocks | Yoshihiro Shimoda | 2022-06-17 | 1 | -0/+2 |
| * | clk: renesas: r8a779f0: Add Z0 and Z1 clock support | Geert Uytterhoeven | 2022-06-17 | 1 | -0/+2 |
| * | clk: renesas: rza1: Remove struct rz_cpg | Geert Uytterhoeven | 2022-06-13 | 1 | -18/+15 |
| * | clk: renesas: r8a7779: Remove struct r8a7779_cpg | Geert Uytterhoeven | 2022-06-13 | 1 | -18/+9 |
| * | clk: renesas: r8a7778: Remove struct r8a7778_cpg | Geert Uytterhoeven | 2022-06-13 | 1 | -22/+9 |
| * | clk: renesas: sh73a0: Remove sh73a0_cpg.reg | Geert Uytterhoeven | 2022-06-13 | 1 | -13/+13 |
| * | clk: renesas: r8a7740: Remove r8a7740_cpg.reg | Geert Uytterhoeven | 2022-06-13 | 1 | -10/+10 |
| * | clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg | Geert Uytterhoeven | 2022-06-13 | 1 | -11/+11 |
