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path: root/drivers/clk/renesas
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| * | clk: renesas: r8a77970: Add RPC clocksSergei Shtylyov2018-11-051-0/+4
| * | clk: renesas: r7s9210: Add SDHI clocksChris Brandt2018-11-051-0/+5
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* / clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd2018-12-105-8/+8
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* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-1818-168/+1333
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| * clk: renesas: r7s9210: Add SPI clocksChris Brandt2018-09-281-0/+3
| * clk: renesas: r7s9210: Move table update to separate functionChris Brandt2018-09-261-45/+50
| * clk: renesas: r7s9210: Convert some clocks to earlyChris Brandt2018-09-261-6/+26
| * clk: renesas: cpg-mssr: Add early clock supportChris Brandt2018-09-262-21/+89
| * clk: renesas: r8a77970: Add TPU clockSergei Shtylyov2018-09-251-0/+1
| * clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven2018-09-251-2/+2
| * clk: renesas: cpg-mssr: Add r8a774c0 supportFabrizio Castro2018-09-195-0/+299
| * clk: renesas: r8a7743: Add r8a7744 supportBiju Das2018-09-193-2/+18
| * clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt2018-09-115-12/+277
| * clk: renesas: r8a77970: Add TMU clocksSergei Shtylyov2018-09-111-0/+5
| * clk: renesas: r8a77970: Add CMT clocksSergei Shtylyov2018-09-111-0/+4
| * clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy2018-09-111-1/+2
| * clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHISergei Shtylyov2018-09-032-2/+67
| * clk: renesas: r8a77980: Add CMT clocksSergei Shtylyov2018-09-031-0/+4
| * clk: renesas: r8a77990: Add missing I2C7 clockGeert Uytterhoeven2018-08-311-0/+1
| * clk: renesas: r8a77965: Add FDP clockHoan Nguyen An2018-08-281-0/+1
| * clk: renesas: cpg-mssr: Add r8a774a1 supportBiju Das2018-08-275-0/+336
| * clk: renesas: r8a77965: Add SATA clockTakeshi Kihara2018-08-271-0/+1
| * clk: renesas: r8a77980: Add RCLK for watchdog timerGeert Uytterhoeven2018-08-271-0/+4
| * clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven2018-08-272-10/+13
| * clk: renesas: r8a77995: Correct RCLK handlingGeert Uytterhoeven2018-08-271-2/+10
| * clk: renesas: r8a77990: Correct RCLK handlingGeert Uytterhoeven2018-08-271-2/+10
| * clk: renesas: rcar-gen3: Add support for RCKSEL clock selectionGeert Uytterhoeven2018-08-272-4/+26
| * clk: renesas: cpg-mssr: Add support for fixed rate clocksGeert Uytterhoeven2018-08-272-0/+8
| * clk: renesas: r8a77980: Add OSC predivider configuration and clockGeert Uytterhoeven2018-08-271-11/+13
| * clk: renesas: r8a77965: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| * clk: renesas: r8a7796: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| * clk: renesas: r8a7795: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| * clk: renesas: rcar-gen3: Add support for OSC EXTAL predividerGeert Uytterhoeven2018-08-272-0/+11
| * clk: renesas: rcar-gen3: Rename rint to .rGeert Uytterhoeven2018-08-273-3/+6
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*-. | Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-nextStephen Boyd2018-10-1810-28/+28
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| * | clk: Convert to using %pOFn instead of device_node.nameRob Herring2018-08-3010-28/+28
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* | clk: renesas: Convert to SPDX identifiersKuninori Morimoto2018-09-2821-89/+25
* | clk: renesas: use SPDX identifier for Renesas driversWolfram Sang2018-08-308-32/+8
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* clk: renesas: Renesas R9A06G032 clock driverMichel Pollet2018-06-253-0/+900
* clk: renesas: r8a7795: Add CCREE clockGilad Ben-Yossef2018-06-191-0/+1
* clk: renesas: r8a7795: Add CR clockGeert Uytterhoeven2018-06-191-0/+1
* treewide: kzalloc() -> kcalloc()Kees Cook2018-06-124-4/+4
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-06-0914-6/+578
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| * clk: renesas: cpg-mssr: Add support for R-Car E3Yoshihiro Shimoda2018-05-095-0/+302
| * clk: renesas: rcar-gen2: Centralize quirks handlingGeert Uytterhoeven2018-04-161-4/+16
| * clk: renesas: r8a77980: Correct parent clock of PCIEC0Geert Uytterhoeven2018-04-161-1/+1
| * clk: renesas: r8a7794: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| * clk: renesas: r8a7792: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| * clk: renesas: r8a7791/r8a7793: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
| * clk: renesas: r8a7745: Fix LB clock dividerGeert Uytterhoeven2018-04-161-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 14:34:12 +0000