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path: root/drivers/clk/renesas
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* clk: renesas: r9a09g057: Add clock and reset entries for GICLad Prabhakar2025-01-071-0/+4
* clk: renesas: r9a09g057: Add reset entry for SYSLad Prabhakar2025-01-071-0/+1
* clk: renesas: r8a779g0: Add VSPX clocksJacopo Mondi2025-01-071-0/+2
* clk: renesas: r8a779g0: Add FCPVX clocksJacopo Mondi2025-01-071-0/+2
* clk: renesas: r9a09g047: Add I2C clocks/resetsBiju Das2025-01-071-0/+32
* clk: renesas: r9a09g047: Add CA55 core clocksBiju Das2025-01-071-0/+16
* clk: renesas: rzv2h: Add support for RZ/G3E SoCBiju Das2025-01-075-1/+116
* clk: renesas: rzv2h: Add MSTOP supportBiju Das2025-01-073-79/+252
* clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ...Claudiu Beznea2024-12-101-0/+7
* clk: renesas: r8a779h0: Add display clocksTomi Valkeinen2024-12-101-0/+4
* clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resetsLad Prabhakar2024-12-102-0/+51
* clk: renesas: rzv2h: Add selective Runtime PM support for clocksLad Prabhakar2024-12-102-7/+49
* clk: renesas: r9a06g032: Use BIT macro consistentlyWolfram Sang2024-12-101-1/+1
* clk: renesas: r9a06g032: Add restart handlerWolfram Sang2024-12-101-0/+27
* clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining ...Claudiu Beznea2024-12-031-0/+20
* clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSIClaudiu Beznea2024-12-031-0/+20
* clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()Javier Carrasco2024-12-031-1/+1
* clk: renesas: vbattb: Add VBATTB clock driverClaudiu Beznea2024-11-063-0/+211
* clk: renesas: rzg2l: Fix FOUTPOSTDIV clkBiju Das2024-11-031-5/+6
* clk: renesas: r9a08g045: Add power domain for RTCClaudiu Beznea2024-10-251-0/+2
* clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safeClaudiu Beznea2024-10-251-2/+3
* clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local onesClaudiu Beznea2024-10-253-43/+24
* clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()Claudiu Beznea2024-10-251-18/+23
* clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocksGeert Uytterhoeven2024-10-141-6/+4
* clk: renesas: r9a09g057: Add clock and reset entries for ICUFabrizio Castro2024-10-071-0/+2
* clk: renesas: r9a09g057: Add CA55 core clocksLad Prabhakar2024-10-072-0/+21
* clk: renesas: Remove duplicate and trailing empty linesMarek Vasut2024-10-017-8/+0
* clk: Switch back to struct platform_driver::remove()Uwe Kleine-König2024-09-211-1/+1
*-. Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-nextStephen Boyd2024-09-2114-187/+1526
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| | * clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDTLad Prabhakar2024-09-022-0/+88
| | * clk: renesas: rzv2h: Add support for dynamic switching divider clocksLad Prabhakar2024-09-022-3/+201
| | * clk: renesas: r9a08g045: Add clocks, resets and power domains for USBClaudiu Beznea2024-09-021-0/+17
| | * clk: renesas: r8a779h0: Add CANFD clockCong Dang2024-08-201-0/+1
| | * clk: renesas: Add RZ/V2H(P) CPG driverLad Prabhakar2024-08-205-0/+94
| | * clk: renesas: Add family-specific clock driver for RZ/V2H(P)Lad Prabhakar2024-08-024-0/+838
| | * clk: renesas: r8a779h0: Add PWM clockCong Dang2024-08-021-0/+1
| | * clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configsGeert Uytterhoeven2024-07-305-28/+20
| | * clk: renesas: rcar-gen4: Remove unused fixed PLL clock typesGeert Uytterhoeven2024-07-302-24/+0
| | * clk: renesas: rcar-gen4: Remove unused variable PLL2 clock typeGeert Uytterhoeven2024-07-302-10/+0
| | * clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLsGeert Uytterhoeven2024-07-301-5/+5
| | * clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLsGeert Uytterhoeven2024-07-301-7/+7
| | * clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLsGeert Uytterhoeven2024-07-301-6/+6
| | * clk: renesas: r8a779a0: Use defines for PLL control registersGeert Uytterhoeven2024-07-301-4/+9
| | * clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLsGeert Uytterhoeven2024-07-302-0/+44
| | * clk: renesas: rcar-gen4: Add support for fixed variable PLLsGeert Uytterhoeven2024-07-302-10/+26
| | * clk: renesas: rcar-gen4: Add support for variable fractional PLLsGeert Uytterhoeven2024-07-302-7/+18
| | * clk: renesas: rcar-gen4: Add support for fractional multiplicationGeert Uytterhoeven2024-07-301-16/+55
| | * clk: renesas: rcar-gen4: Use defines for common CPG registersGeert Uytterhoeven2024-07-305-21/+27
| | * clk: renesas: rcar-gen4: Use FIELD_GET()Geert Uytterhoeven2024-07-302-5/+11
| | * clk: renesas: rcar-gen4: Clarify custom PLL clock supportGeert Uytterhoeven2024-07-301-15/+17
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-25 20:43:59 +0000