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path: root/drivers/clk/rockchip
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* clk: rockchip: drop MODULE_ALIAS from rk3399 clock controllerHeiko Stuebner2021-03-211-1/+0
* clk: rockchip: drop parenthesis from ARM || COMPILE_TEST dependsHeiko Stuebner2021-03-211-11/+11
* clk: rockchip: add clock controller for rk3568Elaine Zhang2021-03-214-1/+1762
* clk: rockchip: support more core div settingElaine Zhang2021-03-2113-77/+98
* clk: rockchip: fix DPHY gate locations on rk3368Heiko Stuebner2021-02-061-2/+2
* clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368Heiko Stuebner2021-02-061-1/+1
* clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368Heiko Stuebner2021-02-061-2/+2
* clk: rockchip: Demote non-conformant kernel-doc header in half-dividerLee Jones2021-01-261-1/+1
* clk: rockchip: Demote kernel-doc abuses to standard comment blocks in pllsLee Jones2021-01-261-3/+3
* clk: rockchip: Remove unused/undocumented struct members from clk-cpuLee Jones2021-01-261-4/+0
* clk: rockchip: Demote non-conformant kernel-doc headers in main clock codeLee Jones2021-01-261-2/+2
* clk: rockchip: fix i2s gate bits on rk3066 and rk3188Johan Jonker2020-11-291-3/+4
* clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocksJohan Jonker2020-11-291-14/+14
* clk: rockchip: Remove redundant null check before clk_prepare_enableXu Wang2020-11-291-2/+1
* clk: rockchip: Add appropriate arch dependenciesRobin Murphy2020-10-261-1/+11
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-10-228-85/+231
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| * clk: rockchip: Initialize hw to error to avoid undefined behaviorStephen Boyd2020-10-071-1/+1
| * clk: rockchip: rk3399: Support module buildElaine Zhang2020-09-222-1/+57
| * clk: rockchip: fix the clk config to support module buildElaine Zhang2020-09-222-20/+100
| * clk: rockchip: Export some clock common APIs for module driversElaine Zhang2020-09-221-22/+30
| * clk: rockchip: Export rockchip_register_softrst()Elaine Zhang2020-09-221-3/+4
| * clk: rockchip: Export rockchip_clk_register_ddrclk()Elaine Zhang2020-09-221-0/+1
| * clk: rockchip: Use clk_hw_register_composite instead of clk_register_composit...Elaine Zhang2020-09-222-39/+40
| * clk: rockchip: rk3308: drop unused mux_timer_src_pKrzysztof Kozlowski2020-09-221-1/+0
* | clk: rockchip: Fix initialization of mux_pll_src_4plls_pNathan Chancellor2020-08-181-1/+1
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* clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocksAlex Bee2020-07-221-0/+1
* clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"Robin Murphy2020-07-081-4/+4
* clk: rockchip: use separate compatibles for rk3288w-cruHeiko Stuebner2020-07-051-2/+19
* clk: rockchip: Handle clock tree for rk3288w variantMylène Josserand2020-06-171-2/+18
* clk: rockchip: convert rk3036 pll type to use internal lock statusHeiko Stuebner2020-06-151-3/+23
* clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeoutHeiko Stuebner2020-06-151-15/+6
* clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeoutHeiko Stuebner2020-06-151-11/+12
* clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocksJustin Swartz2020-04-131-13/+4
* clk: rockchip: fix mmc get phaseJerome Brunet2020-03-061-2/+2
* clk: let init callback return an error codeJerome Brunet2019-12-231-11/+17
* clk: rockchip: protect the pclk_usb_grf as critical on px30Heiko Stuebner2019-11-051-1/+2
* clk: rockchip: add video-related niu clocks as critical on px30Heiko Stuebner2019-11-051-5/+10
* clk: rockchip: move px30 critical clocks to correct clock controllerHeiko Stuebner2019-11-051-4/+4
* clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandcFinley Xiao2019-11-051-4/+40
* clk: rockchip: make clk_half_divider_ops staticBen Dooks (Codethink)2019-10-311-2/+1
* clk: rockchip: Add clock controller for the rk3308Finley Xiao2019-09-053-0/+969
* clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driverNathan Huckleberry2019-07-251-1/+0
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-178-46/+27
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| * clk: rockchip: export HDMIPHY clock on rk3228Heiko Stuebner2019-06-271-1/+1
| * clk: rockchip: add watchdog pclk on rk3328Heiko Stuebner2019-06-271-0/+3
| * clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macroHeiko Stuebner2019-06-154-36/+12
| * clk: rockchip: add a type from SGRF-controlled gate clocksHeiko Stuebner2019-06-141-0/+4
| * clk: rockchip: Remove 48 MHz PLL rate from rk3288Douglas Anderson2019-06-061-1/+0
| * clk: rockchip: add 1.464GHz cpu-clock rate to rk3228Justin Swartz2019-05-201-0/+1
| * clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()Douglas Anderson2019-05-201-3/+3
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 17:01:12 +0000