| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: sunxi-ng: d1: Add CAN bus gates and resets | Fabien Poussin | 2023-01-08 | 1 | -0/+11 |
| * | clk: sunxi-ng: d1: Mark cpux clock as critical | András Szemző | 2023-01-08 | 1 | -1/+1 |
| * | clk: sunxi-ng: d1: Limit PLL rates to stable ranges | Samuel Holland | 2022-08-25 | 1 | -0/+8 |
| * | clk: sunxi-ng: Add support for the D1 SoC clocks | Samuel Holland | 2021-11-23 | 1 | -0/+1390 |
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