linux.git - Linux kernel mainline tree

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: tegra: clk-dfll: Add suspend and resume support	Sowjanya Komatineni	2019-11-11	1	-0/+1
*	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	Thomas Gleixner	2019-05-30	1	-10/+1
*	clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static	Wei Yongjun	2019-02-18	1	-1/+1
*	Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...	Arnd Bergmann	2019-02-15	1	-16/+504
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\| *	clk: tegra: dfll: add CVB tables for Tegra210	Joseph Lo	2019-02-06	1	-0/+426
\| *	clk: tegra: dfll: CVB calculation alignment with the regulator	Joseph Lo	2019-02-06	1	-5/+44
\| *	clk: tegra: dfll: registration for multiple SoCs	Peter De Schrijver	2019-02-06	1	-11/+34
* \|	clk: tegra: dfll: Fix a potential Oop in remove()	Dan Carpenter	2019-01-09	1	-1/+3
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*	clk: tegra: dfll: Fix drvdata overwriting issue	Nicolin Chen	2017-11-01	1	-7/+5
*	clk: tegra: dfll: Use builtin_platform_driver to simplify the code	Wei Yongjun	2016-11-10	1	-6/+1
*	clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modular	Paul Gortmaker	2016-11-04	1	-14/+2
*	clk: tegra: dfll: Reformat CVB frequency table	Thierry Reding	2016-04-28	1	-25/+25
*	clk: tegra: dfll: Properly clean up on failure and removal	Thierry Reding	2016-04-28	1	-4/+27
*	clk: tegra: dfll: Make code more comprehensible	Thierry Reding	2016-04-28	1	-6/+5
*	clk: tegra: dfll: Reference CVB table instead of copying data	Thierry Reding	2016-04-28	1	-14/+9
*	clk: tegra: Add Tegra124 DFLL clocksource platform driver	Tuomas Tynkkynen	2015-07-16	1	-0/+166