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path: root/drivers/clk/tegra
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* clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driverMiaoqian Lin2022-03-111-0/+1
* clk: tegra: Support runtime PM and power domainDmitry Osipenko2021-12-158-54/+420
* clk: tegra: Make vde a child of pll_p on tegra114Dmitry Osipenko2021-12-151-1/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2021-09-022-6/+2
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| * clk: tegra: fix old-style declarationArnd Bergmann2021-08-291-1/+1
| * clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clockDmitry Osipenko2021-08-111-5/+1
* | clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_opsDmitry Osipenko2021-07-271-0/+10
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* clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulatorAlexandru Ardelean2021-06-251-2/+2
* clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()Yang Yingliang2021-06-021-1/+3
* clk: tegra: Don't deassert reset on enabling clocksDmitry Osipenko2021-05-313-13/+1
* clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko2021-05-311-3/+3
* clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttlingDmitry Osipenko2021-05-312-3/+15
* clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko2021-05-311-0/+3
* clk: tegra: Halve SCLK rate on Tegra20Dmitry Osipenko2021-05-311-3/+3
* clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko2021-05-311-5/+4
* clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2021-05-312-25/+58
* clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko2021-05-311-1/+1
* clk: tegra: Don't enable PLLE HW sequencer at initJC Kuo2021-03-241-12/+0
* clk: tegra: Add PLLE HW power sequencer controlJC Kuo2021-03-241-1/+52
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2021-02-222-4/+2
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| * clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s...Lee Jones2021-02-111-0/+1
| * clk: tegra: clk-tegra30: Remove unused variable 'reg'Lee Jones2021-02-111-4/+1
* | Merge tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds2021-02-205-15/+75
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| * | memory: tegra124-emc: Make driver modularDmitry Osipenko2021-01-055-15/+75
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* / clk: tegra30: Add hda clock default rates to clock driverPeter Geis2021-01-121-0/+2
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-12-214-6/+7
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| * clk: tegra: Fix duplicated SE clock entryDmitry Osipenko2020-12-102-1/+2
| * clk: tegra: bpmp: Clamp clock rates on requestsSivaram Nair2020-11-261-3/+3
| * clk: tegra: Do not return 0 on failureNicolin Chen2020-11-201-2/+2
* | clk: tegra: Export Tegra20 EMC kernel symbolsDmitry Osipenko2020-11-061-0/+3
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-10-221-1/+1
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| * clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()Stephen Boyd2020-09-231-1/+1
* | clk: tegra: Fix missing prototype for tegra210_clk_register_emc()Thierry Reding2020-09-211-0/+2
* | clk: tegra: Always program PLL_E when enabledThierry Reding2020-09-211-3/+0
* | clk: tegra: Capitalization fixesThierry Reding2020-09-211-2/+2
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* clk: tegra: pll: Improve PLLM enable-state detectionDmitry Osipenko2020-07-271-5/+15
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-06-1010-32/+700
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| * clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni2020-05-121-0/+7
| * clk: tegra30: Use custom CCLK implementationDmitry Osipenko2020-05-121-2/+4
| * clk: tegra20: Use custom CCLK implementationDmitry Osipenko2020-05-121-2/+5
| * clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko2020-05-122-0/+36
| * clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko2020-05-122-1/+17
| * clk: tegra: Add custom CCLK implementationDmitry Osipenko2020-05-123-2/+188
| * clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo2020-05-121-19/+31
| * clk: tegra: Implement Tegra210 EMC clockJoseph Lo2020-05-123-0/+373
| * clk: tegra: Export functions for EMC clock scalingJoseph Lo2020-05-121-0/+26
| * clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo2020-05-121-0/+11
| * clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding2020-05-124-6/+2
* | clk: tegra: Fix initial rate for pll_a on Tegra124Thierry Reding2020-05-121-1/+1
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* clk: tegra: Use NULL for pointer initializationStephen Boyd2020-03-241-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 14:03:11 +0000