| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: mxl: Fix a clk entry by adding relevant flags | Rahul Tanwar | 2022-10-17 | 1 | -2/+3 |
| * | clk: mxl: Add option to override gate clks | Rahul Tanwar | 2022-10-17 | 1 | -1/+15 |
| * | clk: mxl: Remove redundant spinlocks | Rahul Tanwar | 2022-10-17 | 1 | -71/+9 |
| * | clk: mxl: Switch from direct readl/writel based IO to regmap based IO | Rahul Tanwar | 2022-10-17 | 1 | -2/+3 |
| * | clk: intel: Avoid unnecessary memset by improving code | Rahul Tanwar | 2020-07-24 | 1 | -4/+3 |
| * | clk: intel: Improve locking in the driver | Rahul Tanwar | 2020-07-24 | 1 | -12/+5 |
| * | clk: intel: Use devm_clk_hw_register() instead of clk_hw_register() | Rahul Tanwar | 2020-07-24 | 1 | -4/+4 |
| * | clk: intel: remove redundant initialization of variable rate64 | Colin Ian King | 2020-05-28 | 1 | -1/+1 |
| * | clk: intel: Add CGU clock driver for a new SoC | Rahul Tanwar | 2020-05-26 | 1 | -0/+636 |
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