summaryrefslogtreecommitdiffstats
path: root/drivers/clk/x86
Commit message (Expand)AuthorAgeFilesLines
* clk: mxl: syscon_node_to_regmap() returns error pointersRahul Tanwar2022-10-261-1/+1
* clk: mxl: Fix a clk entry by adding relevant flagsRahul Tanwar2022-10-173-4/+6
* clk: mxl: Add option to override gate clksRahul Tanwar2022-10-172-1/+16
* clk: mxl: Remove redundant spinlocksRahul Tanwar2022-10-174-91/+9
* clk: mxl: Switch from direct readl/writel based IO to regmap based IORahul Tanwar2022-10-175-29/+42
* platform/x86: Drop the PMC_ATOM Kconfig optionHans de Goede2022-06-121-3/+1
* clk: x86: Fix clk_gate_flags for RV_CLK_GATEAjit Kumar Pandey2022-01-061-1/+1
* clk: x86: Use dynamic con_id string during clk registrationAjit Kumar Pandey2022-01-061-2/+2
* x86: clk: clk-fch: Add support for newer family of AMD's SOCAjit Kumar Pandey2022-01-061-11/+31
* clk: x86: Rename clk-lpt to more specific clk-lpss-atomAndy Shevchenko2021-07-272-7/+7
* Merge tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/r...Linus Torvalds2020-08-153-79/+102
|\
| * clk: x86: Support RV architectureAkshu Agrawal2020-08-071-15/+38
| * clk: x86: Change name from ST to FCHAkshu Agrawal2020-08-072-13/+13
| * ACPI: APD: Change name from ST to FCHAkshu Agrawal2020-08-071-2/+2
* | clk: intel: Avoid unnecessary memset by improving codeRahul Tanwar2020-07-241-4/+3
* | clk: intel: Improve locking in the driverRahul Tanwar2020-07-241-12/+5
* | clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()Rahul Tanwar2020-07-242-5/+5
|/
* clk: intel: remove redundant initialization of variable rate64Colin Ian King2020-05-281-1/+1
* clk: intel: Add CGU clock driver for a new SoCRahul Tanwar2020-05-266-0/+1611
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner2019-06-051-9/+1
* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: x86: Add system specific quirk to mark clocks as criticalDavid Müller2019-04-101-3/+11
*-. Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ...Stephen Boyd2019-03-081-1/+1
|\ \
| | * clk: x86: Move clk-lpss.h to platform_data/x86Andy Shevchenko2019-02-221-1/+1
| |/
* / clk: clk-st: avoid clkdev lookup leak at removeMatti Vaittinen2019-02-061-1/+2
|/
* clk: x86: Stop marking clocks as CLK_IS_CRITICALHans de Goede2018-09-171-7/+0
* clk: x86: add "ether_clk" alias for Bay Trail / Cherry TrailHans de Goede2018-09-171-0/+11
* clk: x86: Set default parent to 48MhzAkshu Agrawal2018-08-301-1/+1
* clk: x86: Add ST oscout platform clockAkshu Agrawal2018-05-172-1/+79
* clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione2017-07-181-0/+7
* clk: x86: pmc-atom: Checking for IS_ERR() instead of NULLDan Carpenter2017-05-011-2/+2
* clk: x86: add "mclk" alias for Baytrail/CherrytrailPierre-Louis Bossart2017-04-191-0/+7
* clk: x86: Add Atom PMC platform clocksIrina Tirdea2017-01-262-0/+372
* clk: x86: Remove clkdev.h and clk.h includesStephen Boyd2016-03-031-2/+0
* clk: x86: Remove CLK_IS_ROOTStephen Boyd2016-03-031-1/+1
* clk: x86: drop owner assignment from platform_driversWolfram Sang2014-10-201-1/+0
* ACPI / LPSS: add support for Intel BayTrailMika Westerberg2013-06-191-3/+1
* ACPI / LPSS: register clock device for Lynxpoint DMA properlyRafael J. Wysocki2013-05-141-4/+11
* ACPI / scan: Add special handler for Intel Lynxpoint LPSS devicesRafael J. Wysocki2013-03-214-175/+2
* clk: x86: add support for Lynxpoint LPSS clocksMika Westerberg2013-01-234-0/+223
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 21:15:42 +0000