| Commit message (Expand) | Author | Age | Files | Lines |
* | clk: zynqmp: Add a check for NULL pointer | Shubhrajyoti Datta | 2022-08-22 | 1 | -2/+5 |
* | clk: zynqmp: make bestdiv unsigned | Shubhrajyoti Datta | 2022-08-22 | 1 | -1/+1 |
* | clk: zynqmp: replace warn_once with pr_debug for failed clock ops | Michael Tretter | 2022-01-24 | 1 | -6/+6 |
* | clk: zynqmp: Handle divider specific read only flag | Rajan Vaja | 2021-06-28 | 1 | -1/+9 |
* | clk: zynqmp: Use firmware specific divider clock flags | Rajan Vaja | 2021-06-28 | 1 | -1/+24 |
* | clk: zynqmp: Use firmware specific common clock flags | Rajan Vaja | 2021-06-28 | 1 | -2/+3 |
* | clk: zynqmp: divider: Add missing description for 'max_div' | Lee Jones | 2021-02-11 | 1 | -0/+1 |
* | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2020-06-10 | 1 | -8/+19 |
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| * | clk: zynqmp: Make zynqmp_clk_get_max_divisor static | YueHaibing | 2020-05-26 | 1 | -1/+1 |
| * | clk: zynqmp: Update fraction clock check from custom type flags | Tejas Patel | 2020-05-26 | 1 | -2/+4 |
| * | clk: zynqmp: Fix divider2 calculation | Tejas Patel | 2020-05-26 | 1 | -5/+12 |
| * | clk: zynqmp: Limit bestdiv with maxdiv | Rajan Vaja | 2020-05-26 | 1 | -0/+2 |
* | | firmware: xilinx: Remove eemi ops for clock_getdivider | Rajan Vaja | 2020-04-28 | 1 | -4/+2 |
* | | firmware: xilinx: Remove eemi ops for clock_setdivider | Rajan Vaja | 2020-04-28 | 1 | -2/+1 |
* | | firmware: xilinx: Remove eemi ops for query_data | Rajan Vaja | 2020-04-28 | 1 | -2/+1 |
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* | clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag | Tejas Patel | 2020-01-23 | 1 | -5/+31 |
* | clk: zynqmp: Fix divider calculation | Rajan Vaja | 2020-01-23 | 1 | -0/+46 |
* | clk: zynqmp: Add support for get max divider | Rajan Vaja | 2020-01-23 | 1 | -0/+36 |
* | clk: zynqmp: fix check for fractional clock | Michael Tretter | 2019-04-11 | 1 | -3/+6 |
* | clk: zynqmp: do not export zynqmp_clk_register_* functions | Michael Tretter | 2019-04-11 | 1 | -1/+0 |
* | drivers: clk: zynqmp: Allow zero divisor value | Rajan Vaja | 2019-04-11 | 1 | -0/+7 |
* | drivers: clk: Add ZynqMP clock driver | Jolly Shah | 2018-10-09 | 1 | -0/+217 |