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| | | | | | * | | clk: imx8mp: add clkout1/2 supportLucas Stach2022-05-021-0/+14
| | | | | | * | | clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usageMiaoqian Lin2022-05-021-1/+1
| | | | | | * | | clk: imx8mp: Add DISP2 pixel clockMarek Vasut2022-04-181-2/+3
| | | | | | * | | clk: imx: scu: fix a potential memory leak in __imx_clk_gpr_scu()Xiaoke Wang2022-04-121-1/+3
| | | | | | * | | clk: imx: Add check for kcallocJiasheng Jiang2022-04-121-0/+2
| | | | | | * | | clk: imx8mn: add GPT supportAlvin Šipraga2022-04-121-0/+38
| | | | | | * | | clk: imx: Remove the snvs clockJacky Bai2022-04-125-5/+0
| | | | | | * | | clk: imx8m: check mcore_booted before register clkPeng Fan2022-04-121-8/+11
| | | | | | * | | clk: imx: add mcore_booted module paratemterPeng Fan2022-04-126-0/+12
| | | | | | * | | clk: imx8mq: add 27m phy pll ref clockPeng Fan2022-04-071-1/+1
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| | | | | * | | clk: sunxi-ng: h616: Add PLL derived 32KHz clockAndre Przywara2022-05-062-1/+9
| | | | | * | | clk: sunxi-ng: h6-r: Add RTC gate clockAndre Przywara2022-05-062-1/+6
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| | | | * | | clk: tegra: Update kerneldoc to match prototypesThierry Reding2022-05-061-4/+4
| | | | * | | clk: tegra: Replace .round_rate() with .determine_rate()Rajkumar Kasirajan2022-05-041-5/+10
| | | | * | | clk: tegra: Register clocks from root to leafTimo Alho2022-05-041-16/+56
| | | | * | | clk: tegra: Add missing reset deassertionDiogo Ivo2022-05-041-0/+12
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| | | * | | clk: mediatek: mt8173: Switch to clk_hw provider APIsChen-Yu Tsai2022-05-191-5/+4
| | | * | | clk: mediatek: Switch to clk_hw provider APIsChen-Yu Tsai2022-05-198-122/+123
| | | * | | clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai2022-05-1994-444/+438
| | | * | | clk: mediatek: apmixed: Drop error message from clk_register() failureChen-Yu Tsai2022-05-191-3/+1
| | | * | | clk: mediatek: Make mtk_clk_register_composite() staticChen-Yu Tsai2022-05-192-4/+1
| | | * | | clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen2022-05-1814-131/+127
| | | * | | clk: mediatek: update compatible string for MT7986 ethsysSam Shih2022-05-181-1/+1
| | | * | | clk: mediatek: Add MT8186 ipesys clock supportChun-Jie Chen2022-04-252-1/+56
| | | * | | clk: mediatek: Add MT8186 mdpsys clock supportChun-Jie Chen2022-04-252-1/+81
| | | * | | clk: mediatek: Add MT8186 camsys clock supportChun-Jie Chen2022-04-252-1/+92
| | | * | | clk: mediatek: Add MT8186 vencsys clock supportChun-Jie Chen2022-04-252-1/+52
| | | * | | clk: mediatek: Add MT8186 vdecsys clock supportChun-Jie Chen2022-04-252-1/+89
| | | * | | clk: mediatek: Add MT8186 imgsys clock supportChun-Jie Chen2022-04-252-1/+70
| | | * | | clk: mediatek: Add MT8186 wpesys clock supportChun-Jie Chen2022-04-252-1/+52
| | | * | | clk: mediatek: Add MT8186 mmsys clock supportChun-Jie Chen2022-04-252-1/+112
| | | * | | clk: mediatek: Add MT8186 mfgsys clock supportChun-Jie Chen2022-04-252-1/+50
| | | * | | clk: mediatek: Add MT8186 imp i2c wrapper clock supportChun-Jie Chen2022-04-252-1/+68
| | | * | | clk: mediatek: Add MT8186 apmixedsys clock supportChun-Jie Chen2022-04-252-1/+135
| | | * | | clk: mediatek: Add MT8186 infrastructure clock supportChun-Jie Chen2022-04-252-1/+217
| | | * | | clk: mediatek: Add MT8186 topckgen clock supportChun-Jie Chen2022-04-252-1/+781
| | | * | | clk: mediatek: Add MT8186 mcusys clock supportChun-Jie Chen2022-04-253-0/+117
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| | * | | clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base()Hangyu Hua2022-05-181-1/+1
| | * | | clk: ux500: Implement the missing CLKOUT clocksLinus Walleij2022-04-253-7/+199
| | * | | clk: ux500: Rewrite PRCMU clocks to use clk_hw_*Linus Walleij2022-04-253-209/+183
| | * | | clk: ux500: Drop .is_prepared state from PRCMU clocksLinus Walleij2022-04-251-27/+2
| | * | | clk: ux500: Drop .is_enabled state from PRCMU clocksLinus Walleij2022-04-251-35/+0
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| *-----. \ \ Merge branches 'clk-ti', 'clk-cleanup', 'clk-airoha', 'clk-i2c-simple' and 'c...Stephen Boyd2022-05-2544-185/+1860
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| | | | | * | | clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy2022-05-061-5/+9
| | | | | * | | clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy2022-05-065-0/+181
| | | | | * | | clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy2022-05-052-3/+17
| | | | | * | | clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy2022-05-054-1/+16
| | | | | * | | clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy2022-05-053-31/+19
| | | | | * | | clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy2022-05-053-6/+12
| | | | | * | | clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy2022-05-053-22/+19
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