summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/acpi.c
Commit message (Expand)AuthorAgeFilesLines
* cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang2024-01-051-4/+2
* cxl: Store the access coordinates for the generic portsDave Jiang2023-12-221-0/+25
* cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang2023-12-221-3/+129
* cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang2023-10-271-0/+3
* cxl/acpi: Annotate struct cxl_cxims_data with __counted_byKees Cook2023-09-221-2/+2
* cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()Breno Leitao2023-07-181-1/+1
* cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()Breno Leitao2023-07-181-2/+1
* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-251-90/+116
|\
| * cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's portRobert Richter2023-06-251-28/+63
| * cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()Robert Richter2023-06-251-45/+45
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-251-30/+21
* | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams2023-06-251-1/+1
|/
* Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams2023-02-101-1/+2
|\
| * cxl/dax: Create dax devices for CXL RAM regionsDan Williams2023-02-101-1/+2
* | Merge branch 'for-6.3/cxl' into cxl/nextDan Williams2023-02-071-1/+1
|\ \
| * | cxl: fix spelling mistakesRandy Dunlap2023-01-261-1/+1
| |/
* / cxl/pmem: Fix nvdimm unregistration when cxl_pmem driver is absentDan Williams2023-01-251-1/+0
|/
* cxl: update names for interleave ways conversion macrosDave Jiang2022-12-051-3/+3
* cxl: update names for interleave granularity conversion macrosDave Jiang2022-12-051-2/+2
* cxl/acpi: Warn about an invalid CHBCR in an existing CHBS entryRobert Richter2022-12-051-1/+2
* cxl/acpi: Fail decoder add if CXIMS for HBIG is missingAlison Schofield2022-12-051-0/+5
* Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams2022-12-051-3/+134
|\
| * cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield2022-12-031-3/+134
* | cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter2022-12-031-5/+46
* | cxl/ACPI: Register CXL host ports by bridge deviceRobert Richter2022-12-021-18/+20
* | tools/testing/cxl: Make mock CEDT parsing more robustDan Williams2022-12-021-0/+4
* | cxl/acpi: Move rescan to the workqueueDan Williams2022-12-021-2/+15
* | cxl/acpi: Simplify cxl_nvdimm_bridge probingDan Williams2022-12-011-0/+1
* | cxl/acpi: Improve debug messages in cxl_acpi_probe()Robert Richter2022-11-141-4/+8
* | cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter2022-11-141-5/+2
* | cxl: Unify debug messages when calling devm_cxl_add_port()Robert Richter2022-11-141-2/+0
|/
* cxl/acpi: Minimize granularity for x1 interleavesDan Williams2022-08-011-0/+6
* cxl/acpi: Autoload driver for 'cxl_acpi' test devicesDan Williams2022-08-011-0/+7
* cxl/port: Record parent dport when adding portsDan Williams2022-07-211-2/+1
* cxl/core: Define a 'struct cxl_root_decoder'Dan Williams2022-07-211-4/+36
* cxl/acpi: Track CXL resources in iomem_resourceDan Williams2022-07-211-3/+141
* cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams2022-07-211-1/+3
* cxl: Introduce cxl_to_{ways,granularity}Dan Williams2022-07-091-15/+19
* cxl/core: Drop ->platform_res attribute for root decodersDan Williams2022-07-091-7/+10
* cxl/acpi: Add root device lockdep validationDan Williams2022-04-281-0/+13
* cxl/core/port: Fix / relax decoder target enumerationDan Williams2022-02-081-1/+1
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-081-1/+2
* cxl/core/port: Add switch port enumerationDan Williams2022-02-081-16/+1
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-081-1/+1
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-081-25/+1
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-081-28/+15
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-081-59/+8
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-081-1/+1
* cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2022-02-081-0/+2
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-081-5/+9
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 04:39:51 +0000