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path:
root
/
drivers
/
cxl
/
acpi.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
cxl/acpi: Minimize granularity for x1 interleaves
Dan Williams
2022-08-01
1
-0
/
+6
*
cxl/acpi: Autoload driver for 'cxl_acpi' test devices
Dan Williams
2022-08-01
1
-0
/
+7
*
cxl/port: Record parent dport when adding ports
Dan Williams
2022-07-21
1
-2
/
+1
*
cxl/core: Define a 'struct cxl_root_decoder'
Dan Williams
2022-07-21
1
-4
/
+36
*
cxl/acpi: Track CXL resources in iomem_resource
Dan Williams
2022-07-21
1
-3
/
+141
*
cxl/core: Define a 'struct cxl_switch_decoder'
Dan Williams
2022-07-21
1
-1
/
+3
*
cxl: Introduce cxl_to_{ways,granularity}
Dan Williams
2022-07-09
1
-15
/
+19
*
cxl/core: Drop ->platform_res attribute for root decoders
Dan Williams
2022-07-09
1
-7
/
+10
*
cxl/acpi: Add root device lockdep validation
Dan Williams
2022-04-28
1
-0
/
+13
*
cxl/core/port: Fix / relax decoder target enumeration
Dan Williams
2022-02-08
1
-1
/
+1
*
cxl/mem: Add the cxl_mem driver
Ben Widawsky
2022-02-08
1
-1
/
+2
*
cxl/core/port: Add switch port enumeration
Dan Williams
2022-02-08
1
-16
/
+1
*
cxl/core/port: Remove @host argument for dport + decoder enumeration
Dan Williams
2022-02-08
1
-1
/
+1
*
cxl/port: Add a driver for 'struct cxl_port' objects
Ben Widawsky
2022-02-08
1
-25
/
+1
*
cxl/core/hdm: Add CXL standard decoder enumeration to the core
Dan Williams
2022-02-08
1
-28
/
+15
*
cxl/core: Generalize dport enumeration in the core
Dan Williams
2022-02-08
1
-59
/
+8
*
cxl/pci: Rename pci.h to cxlpci.h
Dan Williams
2022-02-08
1
-1
/
+1
*
cxl/port: Up-level cxl_add_dport() locking requirements to the caller
Dan Williams
2022-02-08
1
-0
/
+2
*
cxl/port: Introduce cxl_port_to_pci_bus()
Dan Williams
2022-02-08
1
-5
/
+9
*
cxl: Prove CXL locking
Dan Williams
2022-02-08
1
-5
/
+5
*
cxl/core/port: Make passthrough decoder init implicit
Ben Widawsky
2022-02-08
1
-5
/
+0
*
cxl/core/port: Clarify decoder creation
Ben Widawsky
2022-02-08
1
-2
/
+2
*
cxl/core: Convert decoder range to resource
Ben Widawsky
2022-02-08
1
-14
/
+8
*
cxl/acpi: Map component registers for Root Ports
Ben Widawsky
2022-02-08
1
-2
/
+11
*
ACPI: NUMA: Add a node and memblk for each CFMWS not in SRAT
Alison Schofield
2021-11-15
1
-1
/
+2
*
cxl/test: Mock acpi_table_parse_cedt()
Dan Williams
2021-11-15
1
-0
/
+2
*
cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpers
Dan Williams
2021-11-15
1
-147
/
+87
*
cxl/acpi: Do not fail cxl_acpi_probe() based on a missing CHBS
Alison Schofield
2021-10-08
1
-4
/
+6
*
cxl/core: Split decoder setup into alloc + add
Dan Williams
2021-09-21
1
-24
/
+60
*
cxl/bus: Populate the target list at decoder create
Dan Williams
2021-09-21
1
-1
/
+12
*
tools/testing/cxl: Introduce a mocked-up CXL port hierarchy
Dan Williams
2021-09-21
1
-15
/
+21
*
cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge ports
Alison Schofield
2021-09-07
1
-4
/
+8
*
cxl/acpi: Use the ACPI CFMWS to create static decoder objects
Alison Schofield
2021-06-17
1
-0
/
+122
*
cxl/acpi: Add the Host Bridge base address to CXL port objects
Alison Schofield
2021-06-17
1
-5
/
+95
*
cxl/pmem: Add initial infrastructure for pmem support
Dan Williams
2021-06-15
1
-2
/
+35
*
cxl/acpi: Introduce cxl_decoder objects
Dan Williams
2021-06-09
1
-1
/
+19
*
cxl/acpi: Enumerate host bridge root ports
Dan Williams
2021-06-09
1
-1
/
+92
*
cxl/acpi: Add downstream port data to cxl_port instances
Dan Williams
2021-06-09
1
-1
/
+42
*
cxl/acpi: Introduce the root of a cxl_port topology
Dan Williams
2021-06-09
1
-0
/
+39