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path: root/drivers/cxl/core
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* cxl/region: Fix x1 root-decoder granularity calculationsJim Harris2023-10-271-1/+8
* cxl/region: Fix cxl_region_rwsem lock held when returning to user spaceLi Zhijian2023-10-271-1/+1
* cxl/region: Use cxl_calc_interleave_pos() for auto-discoveryAlison Schofield2023-10-271-112/+15
* cxl/region: Calculate a target position in a region interleaveAlison Schofield2023-10-271-0/+127
* cxl/region: Prepare the decoder match range helper for reuseAlison Schofield2023-10-261-6/+11
* cxl/region: Do not try to cleanup after cxl_region_setup_targets() failsJim Harris2023-10-241-7/+7
* cxl/mem: Fix shutdown orderDan Williams2023-10-091-1/+1
* cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams2023-10-066-48/+82
* cxl/pci: Fix sanitize notifier setupDan Williams2023-10-061-42/+44
* cxl/pci: Clarify devm host for memdev relative setupDan Williams2023-10-061-8/+8
* cxl/pci: Remove inconsistent usage of dev_err_probe()Dan Williams2023-10-061-11/+2
* cxl/pci: Cleanup 'sanitize' to always pollDan Williams2023-09-291-2/+1
* cxl/port: Fix cxl_test register enumeration regressionDan Williams2023-09-221-4/+9
* cxl/region: Refactor granularity select in cxl_port_setup_targets()Alison Schofield2023-09-141-9/+8
* cxl/region: Match auto-discovered region decoders by HPA rangeAlison Schofield2023-09-141-1/+23
* cxl/mbox: Fix CEL logic for poison and security commandsIra Weiny2023-09-141-11/+12
* cxl/memdev: Only show sanitize sysfs files when supportedDavidlohr Bueso2023-07-282-1/+63
* cxl: Fix one kernel-doc commentYang Li2023-06-291-1/+1
* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-256-84/+239
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| * cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2023-06-251-0/+11
| * cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2023-06-251-0/+27
| * cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter2023-06-251-0/+7
| * cxl/regs: Remove early capability checks in Component Register setupRobert Richter2023-06-251-8/+0
| * cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2023-06-251-1/+0
| * cxl/pci: Refactor component register discovery for reuseTerry Bowman2023-06-251-0/+77
| * cxl/core/regs: Add @dev to cxl_register_mapRobert Richter2023-06-252-8/+14
| * cxl: Rename 'uport' to 'uport_dev'Dan Williams2023-06-253-53/+60
| * cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter2023-06-252-12/+12
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-253-5/+8
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-253-9/+35
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-255-6/+141
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| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-305-0/+88
| * | cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron2023-05-301-6/+53
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* | Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams2023-06-251-39/+63
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| * | cxl/region: Fix state transitions after reset failureDan Williams2023-06-251-11/+15
| * | cxl/region: Flag partially torn down regions as unusableDan Williams2023-06-251-0/+12
| * | cxl/region: Move cache invalidation before region teardown, and before setupDan Williams2023-06-251-29/+37
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* | Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams2023-06-258-262/+302
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| * | Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams2023-06-251-23/+4
| * | cxl/memdev: Formalize endpoint port linkageDan Williams2023-06-253-5/+6
| * | cxl/region: Manage decoder target_type at decoder-attach timeDan Williams2023-06-251-0/+12
| * | cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams2023-06-251-9/+26
| * | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams2023-06-253-9/+10
| * | cxl/memdev: Make mailbox functionality optionalDan Williams2023-06-252-1/+10
| * | cxl/mbox: Move mailbox related driver state to its own data structureDan Williams2023-06-252-150/+163
| * | cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams2023-06-251-4/+4
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* | Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxlDan Williams2023-06-251-0/+308
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| * | cxl: add a firmware update mechanism using the sysfs firmware loaderVishal Verma2023-06-251-0/+308
* | | Merge branch 'for-6.5/cxl-background' into for-6.5/cxlDan Williams2023-06-252-1/+199
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| * | cxl/mem: Support Secure EraseDavidlohr Bueso2023-06-252-1/+33
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