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path: root/drivers/cxl/core
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* cxl: Replace lockdep_mutex with local lock classesDan Williams2022-04-283-4/+18
* cxl/mbox: fix logical vs bitwise typoDan Carpenter2022-04-281-1/+1
* cxl/mbox: Replace NULL check with IS_ERR() after vmemdup_user()Alison Schofield2022-04-221-1/+1
* cxl/mbox: Use type __u32 for mailbox payload sizesAlison Schofield2022-04-221-13/+15
* PM: CXL: Disable suspendDan Williams2022-04-222-0/+25
* cxl/mbox: Use new return_code handlingDavidlohr Bueso2022-04-121-2/+1
* cxl/mbox: Improve handling of mbox_cmd hw return codesDavidlohr Bueso2022-04-121-1/+1
* cxl/mbox: Drop mbox_mutex commentDavidlohr Bueso2022-04-121-1/+1
* cxl/mbox: Block immediate mode in SET_PARTITION_INFO commandAlison Schofield2022-04-121-0/+41
* cxl/mbox: Move cxl_mem_command param to a local variableAlison Schofield2022-04-121-12/+8
* cxl/mbox: Make handle_mailbox_cmd_from_user() use a mbox paramAlison Schofield2022-04-121-27/+17
* cxl/mbox: Remove dependency on cxl_mem_command for a debug msgAlison Schofield2022-04-121-3/+14
* cxl/mbox: Construct a users cxl_mbox_cmd in the validation pathAlison Schofield2022-04-121-4/+17
* cxl/mbox: Move build of user mailbox cmd to a helper functionsAlison Schofield2022-04-121-25/+45
* cxl/mbox: Move raw command warning to raw command validationAlison Schofield2022-04-121-3/+2
* cxl/mbox: Move cxl_mem_command construction to helper funcsAlison Schofield2022-04-121-71/+76
* cxl/core/port: Fix NULL but dereferenced coccicheck errorWan Jiabing2022-03-221-1/+4
* cxl/port: Hold port reference until decoder releaseDan Williams2022-02-171-0/+4
* cxl/port: Fix endpoint refcount leakDan Williams2022-02-171-1/+2
* cxl/core: Fix cxl_device_lock() class detectionDan Williams2022-02-111-1/+1
* cxl/core/port: Fix unregister_port() lock assertionDan Williams2022-02-111-4/+20
* cxl/regs: Fix size of CXL Capability Header RegisterJonathan Cameron2022-02-081-2/+2
* cxl/core/port: Handle invalid decodersDan Williams2022-02-081-6/+30
* cxl/core/port: Fix / relax decoder target enumerationDan Williams2022-02-081-1/+4
* cxl/core/port: Add endpoint decodersBen Widawsky2022-02-082-8/+63
* cxl/core: Move target_list out of base decoder attributesDan Williams2022-02-081-1/+2
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-082-4/+117
* cxl/core/port: Add switch port enumerationDan Williams2022-02-081-9/+418
* cxl/memdev: Add numa_node attributeDan Williams2022-02-081-0/+17
* cxl/pci: Emit device serial numberDan Williams2022-02-081-0/+11
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-083-14/+14
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-082-4/+32
* cxl/core: Emit modalias for CXL devicesDan Williams2022-02-081-9/+17
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-085-15/+298
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-083-39/+154
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-081-1/+1
* cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2022-02-081-2/+1
* cxl/pmem: Introduce a find_cxl_root() helperDan Williams2022-02-082-4/+59
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-081-0/+37
* cxl/core/port: Use dedicated lock for decoder target listDan Williams2022-02-081-7/+23
* cxl: Prove CXL lockingDan Williams2022-02-082-13/+38
* cxl/core: Track port depthBen Widawsky2022-02-081-0/+2
* cxl/core/port: Make passthrough decoder init implicitBen Widawsky2022-02-081-1/+8
* cxl/core: Fix cxl_probe_component_regs() error messageDan Williams2022-02-081-1/+1
* cxl/core/port: Clarify decoder creationBen Widawsky2022-02-081-8/+75
* cxl/core: Convert decoder range to resourceBen Widawsky2022-02-081-2/+21
* cxl/decoder: Hide physical address information from non-rootDan Williams2022-02-081-1/+1
* cxl/core/port: Rename bus.c to port.cDan Williams2022-02-082-1/+1
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-081-0/+56
* cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor2022-01-041-4/+2
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