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path: root/drivers/cxl/pci.c
Commit message (Expand)AuthorAgeFilesLines
* cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()Smita Koralahalli2023-09-111-2/+1
* cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registersSmita Koralahalli2023-09-111-3/+3
* cxl/pci: Use correct flag for sanitize pollingDavidlohr Bueso2023-06-271-1/+1
* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-251-75/+46
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| * cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter2023-06-251-9/+48
| * cxl/regs: Remove early capability checks in Component Register setupRobert Richter2023-06-251-0/+2
| * cxl/pci: Refactor component register discovery for reuseTerry Bowman2023-06-251-74/+5
| * cxl/core/regs: Add @dev to cxl_register_mapRobert Richter2023-06-251-12/+11
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-251-1/+25
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| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-301-1/+25
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* | Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams2023-06-251-93/+87
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| * | cxl/pci: Unconditionally unmask 256B Flit errorsDan Williams2023-06-251-16/+2
| * | cxl/mbox: Move mailbox related driver state to its own data structureDan Williams2023-06-251-53/+61
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* | Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxlDan Williams2023-06-251-0/+4
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| * | cxl: add a firmware update mechanism using the sysfs firmware loaderVishal Verma2023-06-251-0/+4
* | | cxl/mem: Wire up Sanitization supportDavidlohr Bueso2023-06-251-0/+6
* | | cxl/mbox: Add sanitization handling machineryDavidlohr Bueso2023-06-251-3/+74
* | | cxl/mbox: Allow for IRQ_NONE case in the isrDavidlohr Bueso2023-06-251-2/+4
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* | cxl/mbox: Add background cmd handling machineryDavidlohr Bueso2023-05-231-0/+89
* | cxl/pci: Introduce cxl_request_irq()Davidlohr Bueso2023-05-231-16/+23
* | cxl/pci: Allocate irq vectors earlier during probeDavidlohr Bueso2023-05-231-4/+4
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* cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang2023-05-181-0/+6
* Merge branch 'for-6.4/cxl-poison' into for-6.4/cxlDan Williams2023-04-231-0/+4
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| * cxl/mbox: Initialize the poison stateAlison Schofield2023-04-231-0/+4
* | cxl/pci: Use CDAT DOE mailbox created by PCI coreLukas Wunner2023-04-181-49/+0
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* Merge branch 'for-6.3/cxl' into cxl/nextDan Williams2023-02-141-8/+62
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| * cxl: add RAS status unmasking for CXLDave Jiang2023-02-141-0/+65
| * cxl: remove unnecessary calling of pci_enable_pcie_error_reporting()Dave Jiang2023-02-141-11/+0
* | cxl/pci: Fix irq oneshot expectationsDan Williams2023-01-301-1/+2
* | cxl/pci: Set the device timestampJonathan Cameron2023-01-301-0/+4
* | cxl/mem: Wire up event interruptsDavidlohr Bueso2023-01-261-10/+211
* | cxl/mem: Read, trace, and clear events on driver loadIra Weiny2023-01-261-0/+33
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* cxl/pci: Show opcode in debug messages when sending a commandRobert Richter2023-01-241-1/+1
* cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams2023-01-041-111/+0
* cxl/pci: Remove endian confusionDan Williams2022-12-061-4/+3
* cxl/pci: Add some type-safety to the AER trace pointsDan Williams2022-12-061-2/+2
* Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams2022-12-051-40/+173
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| * cxl/pci: Add callback to log AER correctable errorDave Jiang2022-12-031-0/+20
| * cxl/pci: Add (hopeful) error handling supportDan Williams2022-12-031-0/+137
| * cxl/pci: add tracepoint events for CXL RASDave Jiang2022-12-031-0/+2
| * cxl/pci: Find and map the RAS Capability StructureDan Williams2022-12-031-0/+8
| * cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams2022-12-031-19/+6
| * cxl/pci: Kill cxl_map_regs()Dan Williams2022-12-031-22/+1
* | cxl/port: Add RCD endpoint port enumerationDan Williams2022-12-051-0/+10
* | cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams2022-12-021-3/+0
* | cxl/doe: Request exclusive DOE accessIra Weiny2022-11-141-0/+5
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* cxl/pci: Create PCI DOE mailbox's for memory devicesIra Weiny2022-07-191-0/+44
* cxl/mem: Convert partition-info to resourcesDan Williams2022-07-091-1/+1
* cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams2022-05-191-135/+0
* cxl/pci: Move cxl_await_media_ready() to the coreDan Williams2022-05-191-44/+1
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