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* cxl/acpi: Annotate struct cxl_cxims_data with __counted_byKees Cook2023-09-221-2/+2
* cxl/port: Fix cxl_test register enumeration regressionDan Williams2023-09-221-4/+9
* cxl/region: Refactor granularity select in cxl_port_setup_targets()Alison Schofield2023-09-141-9/+8
* cxl/region: Match auto-discovered region decoders by HPA rangeAlison Schofield2023-09-141-1/+23
* cxl/mbox: Fix CEL logic for poison and security commandsIra Weiny2023-09-141-11/+12
* cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()Smita Koralahalli2023-09-111-2/+1
* cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registersSmita Koralahalli2023-09-111-3/+3
* cxl/memdev: Only show sanitize sysfs files when supportedDavidlohr Bueso2023-07-283-1/+78
* cxl/memdev: Document security state in kern-docDavidlohr Bueso2023-07-281-0/+1
* cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()Breno Leitao2023-07-181-1/+1
* cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()Breno Leitao2023-07-181-2/+1
* cxl/mem: Fix a double shift bugDan Carpenter2023-07-141-1/+1
* cxl: fix CONFIG_FW_LOADER dependencyArnd Bergmann2023-07-141-1/+2
* cxl: Fix one kernel-doc commentYang Li2023-06-291-1/+1
* cxl/pci: Use correct flag for sanitize pollingDavidlohr Bueso2023-06-271-1/+1
* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-2512-291/+443
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| * cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2023-06-252-0/+13
| * cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2023-06-252-0/+29
| * cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter2023-06-254-18/+57
| * cxl/mem: Prepare for early RCH dport component register setupRobert Richter2023-06-251-5/+4
| * cxl/regs: Remove early capability checks in Component Register setupRobert Richter2023-06-253-9/+6
| * cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2023-06-252-3/+0
| * cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's portRobert Richter2023-06-251-28/+63
| * cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()Robert Richter2023-06-251-45/+45
| * cxl/pci: Refactor component register discovery for reuseTerry Bowman2023-06-253-74/+83
| * cxl/core/regs: Add @dev to cxl_register_mapRobert Richter2023-06-254-24/+31
| * cxl: Rename 'uport' to 'uport_dev'Dan Williams2023-06-257-63/+71
| * cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter2023-06-253-14/+14
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-254-7/+15
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-256-50/+61
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-2510-7/+224
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| * | perf: CXL Performance Monitoring Unit driverJonathan Cameron2023-06-251-0/+13
| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-309-1/+155
| * | cxl: Add functions to get an instance of / count regblocks of a given typeJonathan Cameron2023-05-302-6/+56
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* | Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams2023-06-252-46/+72
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| * | cxl/region: Fix state transitions after reset failureDan Williams2023-06-251-11/+15
| * | cxl/region: Flag partially torn down regions as unusableDan Williams2023-06-252-0/+20
| * | cxl/region: Move cache invalidation before region teardown, and before setupDan Williams2023-06-252-36/+38
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* | Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams2023-06-2516-445/+515
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| * | Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams2023-06-253-33/+9
| * | cxl/memdev: Formalize endpoint port linkageDan Williams2023-06-254-5/+8
| * | cxl/pci: Unconditionally unmask 256B Flit errorsDan Williams2023-06-251-16/+2
| * | cxl/region: Manage decoder target_type at decoder-attach timeDan Williams2023-06-251-0/+12
| * | cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams2023-06-252-10/+27
| * | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams2023-06-255-12/+13
| * | cxl/memdev: Make mailbox functionality optionalDan Williams2023-06-253-1/+28
| * | cxl/mbox: Move mailbox related driver state to its own data structureDan Williams2023-06-257-271/+312
| * | cxl: Remove leftover attribute documentation in 'struct cxl_dev_state'Dan Williams2023-06-251-1/+0
| * | cxl: Fix kernel-doc warningsDan Williams2023-06-251-3/+3
| * | cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams2023-06-252-6/+6
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