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* drm/amd/display: Disable PSR-SU on eDP panelsTom Chung2025-02-251-1/+2
| | | | | | | | | | | | | | | | | | | | [Why] PSR-SU may cause some glitching randomly on several panels. [How] Temporarily disable the PSR-SU and fallback to PSR1 for all eDP panels. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3388 Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 6deeefb820d0efb0b36753622fb982d03b37b3ad) Cc: stable@vger.kernel.org
* drm/amd/display: Do not wait for PSR disable on vbl enableLeo Li2025-01-101-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Outside of a modeset/link configuration change, we should not have to wait for the panel to exit PSR. Depending on the panel and it's state, it may take multiple frames for it to exit PSR. Therefore, waiting in all scenarios may cause perceived stuttering, especially in combination with faster vblank shutdown. [How] PSR1 disable is hooked up to the vblank enable event, and vice versa. In case of vblank enable, do not wait for panel to exit PSR, but still wait in all other cases. We also avoid a call to unnecessarily change power_opts on disable - this ends up sending another command to dmcub fw. When testing against IGT, some crc tests like kms_plane_alpha_blend and amd_hotplug were failing due to CRC timeouts. This was found to be caused by the early return before HW has fully exited PSR1. Fix this by first making sure we grab a vblank reference, then waiting for panel to exit PSR1, before programming hw for CRC generation. Fixes: 58a261bfc967 ("drm/amd/display: use a more lax vblank enable policy for older ASICs") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3743 Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit aa6713fa2046f4c09bf3013dd1420ae15603ca6f) Cc: stable@vger.kernel.org
* drm/amd/display: Fix possible overflow in integer multiplicationAlex Hung2024-07-011-1/+1
| | | | | | | | | | | | | | | [WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned/siged long long (64 bits). This can be fixed by casting integer to unsigned/siged long long to force 64 bits results. This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add periodic detection for IPSRoman Li2024-04-301-0/+28
| | | | | | | | | | | | | | | | [Why] HPD interrupt cannot be handled in IPS2 state. So if there's a display topology change while system in IPS2 it can be missed. [How] Implement worker to check each 5 sec in IPS for HPD. Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix IPX enablementHamza Mahfooz2024-03-271-3/+5
| | | | | | | | | | | | | We need to re-enable idle power optimizations after entering PSR. Since, we get kicked out of idle power optimizations before entering PSR (entering PSR requires us to write to DCN registers, which isn't allowed while we are in IPS). Fixes: a9b1a4f684b3 ("drm/amd/display: Add more checks for exiting idle in DC") Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix function banner for amdgpu_dm_psr_disable_all()Roman Li2024-03-201-1/+1
| | | | | | | | | | | | | | | [WHY] Incorrect function name in function banner. [HOW] Correct name and brief description. Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add a new DC debug mask for PSR-SUMario Limonciello2023-12-191-0/+3
| | | | | | | | | | | | Some issues have been raised that appear to be tied to PSR-SU. To allow users to confirm they're tied to PSR-SU without turning off PSR entirely introduce a new debug mask: amdgpu.dcdebugmask=0x200 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Clean up warnings in amdgpu_dm _mst_types, _plane, _psr.cSrinivasan Shanmugam2023-07-071-0/+1
| | | | | | | | | | | | | Fix the following warnings reported by checkpatch: WARNING: Missing a blank line after declarations WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Set minimum requirement for using PSR-SU on RembrandtMario Limonciello2023-06-301-1/+2
| | | | | | | | | | | | | | | | | | A number of parade TCONs are causing system hangs when utilized with older DMUB firmware and PSR-SU. Some changes have been introduced into DMUB firmware to add resilience against these failures. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Pass DSC slice height to PSR FWRobin Chen2023-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | [Why] When DSC is enabled, the PSRSU seletive update region must be multiple number of DSC slice height number. The original solution is to overwrite the SU Y granularity by DSC slice height in DAL driver. However, the size of the SU Y granularity variable only has 8 bytes and the DSC slice height may over the 8 bytes size. [How] Instead of overwriting the SU Y granularity value, add a new DSC slice height pararmeter and pass it to DMUB PSRSU FW. The PSRSU FW will refer to the DSC slice height value and extend the SU region. Reviewed-by: Dennis Chan <dennis.chan@amd.com> Reviewed-by: ChunTao Tso <chuntao.tso@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Robin Chen <robin.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix PSR-SU/DSC interoperability supportHamza Mahfooz2023-01-091-0/+3
| | | | | | | | | | | | Currently, there are issues with enabling PSR-SU + DSC. This stems from the fact that DSC imposes a slice height on transmitted video data and we are not conforming to that slice height in PSR-SU regions. So, pass slice_height into su_y_granularity to feed the DSC slice height into PSR-SU code. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: explicitly disable psr_feature_enable appropriatelyShirish S2022-10-101-2/+6
| | | | | | | | | | | | | | | | [Why] If psr_feature_enable is set to true by default, it continues to be enabled for non capable links. [How] explicitly disable the feature on links that are not capable of the same. Fixes: 8c322309e48e9 ("drm/amd/display: Enable PSR") Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.15+
* drm/amd/display: Prevent OTG shutdown during PSR SULeo Li2022-09-291-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Enabling Z10 optimizations allows DMUB to disable the OTG during PSR link-off. This theoretically saves power by putting more of the display hardware to sleep. However, we observe that with PSR SU, it causes visual artifacts, higher power usage, and potential system hang. This is partly due to an odd behavior with the VStartup interrupt used to signal DRM vblank events. If the OTG is toggled on/off during a PSR link on/off cycle, the vstartup interrupt fires twice in quick succession. This generates incorrectly timed vblank events. Additionally, it can cause cursor updates to generate visual artifacts. Note that this is not observed with PSR1 since PSR is fully disabled when there are vblank event requestors. Cursor updates are also artifact-free, likely because there are no selectively-updated (SU) frames that can generate artifacts. [How] A potential solution is to disable z10 idle optimizations only when fast updates (flips & cursor updates) are committed. A mechanism to do so would require some thoughtful design. Let's just disable idle optimizations for PSR2 for now. Fixes: 7cc191ee7621 ("drm/amd/display: Implement MPO PSR SU") Reported-by: August Wikerfors <git@augustwikerfors.se> Link: https://lore.kernel.org/r/c1f8886a-5624-8f49-31b1-e42b6d20dcf5@augustwikerfors.se/ Tested-by: August Wikerfors <git@augustwikerfors.se> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Implement MPO PSR SULeo Li2022-06-061-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] For additional power savings, PSR SU (also referred to as PSR2) can be enabled on eDP panels with PSR SU support. PSR2 saves more power compared to PSR1 by allowing more opportunities for the display hardware to be shut down. In comparison to PSR1, Shut down can now occur in-between frames, as well as in display regions where there is no visible update. In otherwords, it allows for some display hw components to be enabled only for a **selectively updated** region of the visible display. Hence PSR SU. [HOW] To define the SU region, support from the OS is required. OS needs to inform driver of damaged regions that need to be flushed to the eDP panel. Today, such support is lacking in most compositors. Therefore, an in-between solution is to implement PSR SU for MPO and cursor scenarios. The plane bounds can be used to define the damaged region to be flushed to panel. This is achieved by: * Leveraging dm_crtc_state->mpo_requested flag to identify when MPO is enabled. * If MPO is enabled, only add updated plane bounds to dirty region. Determine plane update by either: * Existence of drm damaged clips attached to the plane (added by a damage-aware compositor) * Change in fb id (flip) * Change in plane bounds (position and dimensions) * If cursor is enabled, the old_pos and new_pos of cursor plus cursor size is used as damaged regions(*). (*) Cursor updates follow a different code path through DC. PSR SU for cursor is already implemented in DC, and the only thing required to enable is to set DC_PSR_VERSION_SU_1 on the eDP link. See dcn10_dmub_update_cursor_data(). Signed-off-by: Leo Li <sunpeng.li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: calculate psr config settings in runtime in DMDavid Zhang2022-06-061-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | [why] Currently the psr configuration parameters are hardcoded before feeding into the DC helper before passing to DMUB FW. We'd rework to call a shared helper to calculate/update generic psr config fields which are relying on the stream timing and eDP sink PSR caps to avoid hard-coding. [how] - drop part of hard-coded psr config fields by replacing w/ the call of helper from DM before feeding into DC link setup psr helper - For those DM specific psr config fields, e.g. allow smu opt, is not to be set/updated from the shared helper but to rely on the DC feature mask - for the psr version field in psr_config structure, since only the field psr_version of DC link psr_settings matters for that fed to DMUB FW, thus no need to set/update the psr_version field of psr_config structure. Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in amdgpu_dmAlex Hung2022-05-101-4/+0
| | | | | | | | | | | | | | | [Why & How] CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC code should be OS-agnostic. This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN in amdgpu_dm directory. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: implement shared PSR-SU sink validation helperDavid Zhang2022-04-131-1/+8
| | | | | | | | | | | | | | | | | [why] creating a generic helper for AMD specific PSR-SU sink validation. Moving the function to the power module to reference it across all OS. [how] - drop PSRSU specific sink validation helper and move to power module by reading PSR version and other PSR caps - call the new helper from linux DM (amdgpu_dm_psr) Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: David Zhang <dingchen.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Refactor PSR DPCD caps detectionPo Ting Chen2022-02-231-53/+5
| | | | | | | | | | | [Why] To move the PSR DPCD caps detection into detect_edp_sink_caps() Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Po Ting Chen <robin.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Use PSR version selected during set_psr_capsNicholas Kazlauskas2022-01-251-4/+2
| | | | | | | | | | | | | | | | | | | | [Why] If the DPCD caps specifies a PSR version newer than PSR_VERSION_1 then we fallback to using PSR_VERSION_1 in amdgpu_dm_set_psr_caps. This gets overriden with the raw DPCD value in amdgpu_dm_link_setup_psr, which can result in DMCUB hanging if we pass in an unsupported PSR version number. [How] Fix the hang by using link->psr_settings.psr_version directly during amdgpu_dm_link_setup_psr. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: parse and check PSR SU capsMikita Lipski2021-12-141-13/+88
| | | | | | | | | | | | | | | | | | | | [why] Adding a function to read PSR capabilities and ALPM capabilities. Also adding a helper function to validate if the sink and the driver support PSR SU. [how] - isolated all PSR and ALPM reading calls to a separate funciton - set all required PSR caps - added a helper function to check if PSR SU is supported by sink and the driver Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: dc_link_set_psr_allow_active refactoringRobin Chen2021-10-281-2/+8
| | | | | | | | | | | | | [Why] To expose new power optimization flags to PSR interface. It allows the PSR related power features can be enabled separately base on different use scenarios. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Robin Chen <po-tchen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: remove unused variable 'dc'Pu Lehui2021-06-181-2/+0
| | | | | | | | | | | | | | | | | GCC reports the following warning with W=1: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.c:70:13: warning: variable ‘dc’ set but not used [-Wunused-but-set-variable] 70 | struct dc *dc = NULL; | ^~ This variable is not used in function, this commit remove it to fix the warning. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Pu Lehui <pulehui@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: move psr dm interface to separate filesRoman Li2021-06-151-0/+166
[Why] Improve the maintain/read abilities of dm code. [How] Create amdgpu_dm_psr.c/h files. Move psr function from amdgpu_dm.c Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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