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* Revert "drm/amdgpu/swsmu: drop set_fan_speed_percent (v2)"Alex Deucher2021-02-011-1/+1
| | | | | | | | | | | | On some boards the rpm interface apparently does not work at all leading to the fan not spinning or spinning at strange speeds. Revert this for now to fix 5.10, 5.11. The follow on patch fixes this properly for 5.12. This reverts commit 8d6e65adc25e23fabbc5293b6cd320195c708dca. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1408 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: store and reinstate swsmu user power configurationsArunpravin2021-01-251-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | store swsmu user power configurations which include power limit, clock frequencies, fan speed and fan mode on suspend and reinstate on resume. V2: Addressed Lijo's review comments added a function to set clock interdependencies add check on fan control mode to reapply fan speed V3: Addressed review comments from Alex moved store logic and reinstate function call into swSMU V4: added a logic to keep off storing configurations in suspend V5: Addressed review comments from Lijo add a restore flag give restore priority to mclk comparing fclk and socclk Signed-off-by: Arunpravin <Arunpravin.PaneerSelvam@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix build error without x86 kconfig (v2)Huang Rui2021-01-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to fix below build error while we are using the kconfig without x86. drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_get_smu_metrics_data': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:300:10: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 300 | boot_cpu_data.x86_max_cores * sizeof(uint16_t)); | ^~~~~~~~~~~~~ | boot_cpuid drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_read_sensor': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:1320:11: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 1320 | *size = boot_cpu_data.x86_max_cores * sizeof(uint16_t); | ^~~~~~~~~~~~~ | boot_cpuid drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_od_edit_dpm_table': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:1460:19: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 1460 | if (input[0] >= boot_cpu_data.x86_max_cores) { | ^~~~~~~~~~~~~ | boot_cpuid v2: fix #ifdef and add comment for APU only Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: modify the fine grain tuning function for RenoirXiaojian Du2021-01-141-3/+0
| | | | | | | | | | | | | | | | | | | | | | This patch is to modify the fine grain tuning function for Renoir. The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage to config gfxclk. Meanwhile, another sysfs node -- power_dpm_force_perfomance_level also affects the gfx clk. It will cause confusion when these two sysfs nodes works together. It is risky to add two new flags to common smu struct, so this patch uses the existing flag to make these two sysfs nodes works separately. Only when power_dpm_force_perfomance_level is changed to "manual" mode, the fine grain function will be started. In other profile modes, including "auto", "high", "low", "profile_peak", "profile_standard", "profile_min_sclk", "profile_min_mclk", the fine grain tuning function will be shut down and the frequency range of gfx will be restored the default value. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: implement processor fine grain feature for vangogh (v3)Huang Rui2021-01-131-0/+6
| | | | | | | | | | | | | | | | | | | | | This patch is to implement the processor fine grain feature for vangogh. It's similar with gfx clock, the only difference is below: echo "p core_id level value" > pp_od_clk_voltage 1. "p" - set the cclk (processor) frequency 2. "core_id" - 0/1/2/3, represents which cpu core you want to select 2. "level" - 0 or 1, "0" represents the min value, "1" represents the max value 3. "value" - the target value of cclk frequency, it should be limited in the safe range v2: fix some missing changes as Evan's suggestion. v3: add version check and fix the restore. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: implement the processor clocks which read by metricHuang Rui2021-01-131-0/+2
| | | | | | | | | The core processor clocks will be stored in smu metric table, then we add this runtime information into amdgpu_pm_info interface. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: modify the fine grain tuning function for RenoirXiaojian Du2021-01-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to improve the fine grain tuning function for Renoir. The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage to config gfxclk. Meanwhile, another sysfs node -- power_dpm_force_perfomance_level also affects the gfx clk. It will cause confusion when these two sysfs nodes works together. And the flag "od_enabled" is used to control the overdrive function for dGPU, like navi10, navi14 and navi21. APU like Renior or Vangogh uses this "od_enabled" to configure the frequency range of gfx clock, but the max value of frequency range will not be higher than the safe limit, it is not "overdrive". So this patch adds two new flags -- "fine_grain_enabled" and "fine_grain_started" to avoid this confusion, the flag will make these two sysfs nodes work separately. The flag "fine_grain_enabled" is set as "enabled" by default, so the fine grain tuning function will be enabled by default. But the flag "fine_grain_started" is set as "false" by default, so the fine grain function will not take effect until it is set as "true". Only when power_dpm_force_perfomance_level is changed to "manual" mode, the flag "fine_grain_started" will be set as "true", and the fine grain tuning function will be started. In other profile modes, including "auto", "high", "low", "profile_peak", "profile_standard", "profile_min_sclk", "profile_min_mclk", the flag "fine_grain_started" will be set as "false", and the od range of fine grain tuning function will be restored default value. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: add new feature map macros to resolve duplicate nameXiaojian Du2021-01-051-0/+6
| | | | | | | | | | This patch is to add new feature map macros to resolve duplicate name. Vangogh uses one different format to name some feature bits of swSMU, it causes some duplicate name in the existing feature map list. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: add pptable_funcs documentation (v3)Ryan Taylor2020-12-231-0/+526
| | | | | | | | | | | | Documents the hooks in struct pptable_funcs. v2: Improved documentation accuracy. v3: Improved set_default_od_settings() definition. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: expose the firmware_capability from firmware_info tableEvan Quan2020-12-101-0/+1
| | | | | | | | | That will help to determine whether 2ND_USB20_PORT workaround is needed for Sienna Cichlid. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: add metrics enums for voltageAlex Deucher2020-12-021-0/+2
| | | | | | | | To be used in subsequent patches. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: fix spelling mistake "smu_state_memroy_block" -> ↵Colin Ian King2020-11-241-2/+2
| | | | | | | | | | | | "smu_state_memory_block" The struct name smu_state_memroy_block contains a spelling mistake, rename it to smu_state_memory_block Fixes: 8554e67d6e22 ("drm/amd/powerplay: implement power_dpm_state sys interface for SMU11") Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: add the fine grain tuning function for vangoghXiaojian Du2020-11-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to add the fine grain tuning function for vangogh. This function uses the pp_od_clk_voltage sysfs file to configure the min and max value of gfx clock frequency or restore the default value. Command guide: echo "s level value" > pp_od_clk_voltage "s" - set the sclk frequency "level" - 0 or 1, "0" represents the min value, "1" represents the max value "value" - the target value of sclk frequency, it should be limited in the safe range echo "r" > pp_od_clk_voltage "r" - reset the sclk frequency, restore the default value instantly echo "c" > pp_od_clk_voltage "c" - commit the min and max value of sclk frequency to the system only after the commit command, the setting target values by "s" command will take effect. Example: 1)check the default sclk frequency $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz 2)use "s" -- set command to configure the min or max sclk frequency $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz 3)use "r" -- reset command to restore the min and max sclk frequency $ echo "r" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: add gfx_state_change_set() for rn gfx power switch (v2)Prike Liang2020-11-131-0/+2
| | | | | | | | | | | | The gfx_state_change_set() funtion can support set GFX power change status to D0/D3. v2: make sure to register callback (Alex) Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: properly setting GPO feature on UMD pstate entering/exitingEvan Quan2020-10-151-0/+1
| | | | | | | | Disable/enable the GPO feature on UMD pstate entering/exiting. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: populate the bootup LCLK frequencyEvan Quan2020-10-151-0/+1
| | | | | | | | As for other clock domains. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: increase size for smu fw_name stringTao Zhou2020-10-121-0/+1
| | | | | | | | | | A longer chip name needs more space. v2: define macro for the length of smu fw name Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: clean up a bunch of stale interfacesAlex Deucher2020-10-091-46/+0
| | | | | | | | | These were leftover from the initial implementation, but never used. Drop them. Reviewed-by: Evan Quan <evan.quan@amd.com> Noticed-by: Ryan Taylor <ryan.taylor@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: add interrupt work functionAlex Deucher2020-10-011-0/+2
| | | | | | | | | So we can schedule work from interrupts. This might include long tasks or things that could sleep. Fixes: e1188aacad1730 ("drm/amdgpu/smu11: add support for SMU AC/DC interrupts") Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: drop unnecessary wrappers around watermark settingEvan Quan2020-09-171-2/+2
| | | | | | | | | | The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15" is totally unnecessary and can be dropped. Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: drop unnecessary table existence and dpm enablement checkEvan Quan2020-09-171-1/+0
| | | | | | | | | | Either this was already performed in parent API. Or the table is confirmed to exist. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: allocate a new buffer for pstate dummy readingEvan Quan2020-09-171-0/+1
| | | | | | | | | This dummy reading buffer will be used for the new Navi1x UMC CDR workaround. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: put Navi1X umc cdr workaround in post_smu_initEvan Quan2020-09-171-1/+0
| | | | | | | | | That's where the uclk dpm get enabled and then the uclk cdr workaround can be applied. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: wrapper for postponing some setup job after DAL initializatioa(V2)Evan Quan2020-09-171-0/+1
| | | | | | | | | | So that ASIC specific actions can be added. V2: better namings Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: drop set_fan_speed_percent (v2)Alex Deucher2020-09-031-1/+0
| | | | | | | | | | No longer needed as we can calculate it based on the fan's max rpm. v2: minor code rework Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: drop get_fan_speed_percent (v2)Alex Deucher2020-09-031-1/+0
| | | | | | | | | | | No longer needed as we can calculate it based on the fan's max rpm. v2: rework code to avoid possible uninitialized variable use. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swsmu: add new callback for getting fan parametersAlex Deucher2020-09-031-0/+4
| | | | | | | To fetch the max rpm from pptable. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: disable/enable deep sleep features on UMD pstate enter/exitEvan Quan2020-08-181-0/+1
| | | | | | | | Add deep sleep disablement/enablement on UMD pstate entering/exiting. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exitEvan Quan2020-08-181-0/+1
| | | | | | | | Add gfx ulv disablement/enablement on UMD pstate entering/exiting. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: optimize the power related source code layoutEvan Quan2020-08-141-0/+806
The target is to provide a clear entry point(for power routines). Also this can help to maintain a clear view about the frameworks used on different ASICs. Hopefully all these can make power part more friendly to play with. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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