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path: root/drivers/gpu/drm/i915/display/intel_cdclk.c
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* drm/i915: move comments about FSB straps to proper placeJani Nikula2024-06-171-10/+1
* drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initializationJani Nikula2024-06-171-43/+3
* drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy2024-06-121-1/+1
* drm/i915/cdclk: Plumb the full atomic state deeperVille Syrjälä2024-05-311-25/+35
* drm/i915/xe2hpd: Initial cdclk tableClint Taylor2024-05-031-0/+11
* drm/i915: move max_dotclk_freq to display substructJani Nikula2024-04-091-3/+3
* drm/i915: move skl_preferred_vco_freq to display substructJani Nikula2024-04-091-9/+8
* drm/i915: Use a plain old int for the cdclk/mdclk ratioVille Syrjälä2024-04-041-3/+3
* drm/i915: Use the correct mdclk/cdclk ratio in MBUS updatesVille Syrjälä2024-04-041-0/+11
* drm/i915: Use old mbus_join value when increasing CDCLKStanislav Lisovskiy2024-04-041-0/+6
* drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plan...Ville Syrjälä2024-04-041-13/+6
* drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacksVille Syrjälä2024-04-041-19/+0
* drm/i915/cdclk: Fix voltage_level programming edge caseVille Syrjälä2024-04-041-10/+27
* drm/i915/cdclk: Fix CDCLK programming order when pipes are activeVille Syrjälä2024-04-041-2/+5
* drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changesGustavo Sousa2024-03-131-0/+31
* drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_stateGustavo Sousa2024-03-131-0/+20
* drm/i915/cdclk: Only compute squash waveform when necessaryGustavo Sousa2024-03-131-3/+3
* drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()Gustavo Sousa2024-03-131-1/+14
* drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_tableGustavo Sousa2024-03-131-2/+2
* drm/i915: Reuse RPLU cdclk fns for MTL+Radhakrishna Sripada2024-03-111-9/+2
* drm/i915/cdclk: Document CDCLK componentsGustavo Sousa2024-02-281-0/+26
* drm/i915/cdclk: Rename intel_cdclk_needs_modeset to intel_cdclk_clock_changedGustavo Sousa2024-02-281-7/+6
* drm/i915: Fix doc build issue on intel_cdclk.cRodrigo Vivi2024-02-231-0/+1
* drm/i915/cdclk: Document CDCLK update methodsVille Syrjälä2024-02-161-0/+9
* drm/i915/cdclk: Remove the hardcoded divider from cdclk_compute_crawl_and_squ...Ville Syrjälä2024-02-161-2/+16
* drm/i915/cdclk: Squash waveform is 16 bitsVille Syrjälä2024-02-161-1/+1
* drm/i915/cdclk: Extract cdclk_divider()Ville Syrjälä2024-02-161-14/+17
* drm/i915/cdclk: Re-use bxt_cdclk_ctl() when sanitizingGustavo Sousa2024-01-081-23/+3
* drm/i915/cdclk: Reorder bxt_sanitize_cdclk()Gustavo Sousa2024-01-081-12/+12
* drm/i915/cdclk: Extract bxt_cdclk_ctl()Gustavo Sousa2024-01-081-22/+35
* drm/i915/xe2lpd: Update bxt_sanitize_cdclk()Gustavo Sousa2024-01-081-1/+4
* drm/i915/mtl: Add fake PCH for Meteor LakeHaridhar Kalvala2024-01-031-3/+3
* drm/i915/cdclk: Remove divider field from tablesGustavo Sousa2023-12-201-135/+134
* drm/i915/mtl: Fix voltage_level for cdclk==480MHzVille Syrjälä2023-12-131-1/+1
* drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tablesVille Syrjälä2023-12-131-30/+57
* drm/i915/cdclk: Remove the assumption that cdclk divider==2 when using squashingVille Syrjälä2023-12-131-7/+5
* drm/i915/cdclk: Give the squash waveform length a nameVille Syrjälä2023-12-131-2/+4
* drm/i915/cdclk: s/-1/~0/ when dealing with unsigned valuesVille Syrjälä2023-12-131-2/+2
* drm/i915: Clean up some DISPLAY_VER checksVille Syrjälä2023-11-291-1/+1
* drm/i915/display: Store compressed bpp in U6.4 formatAnkit Nautiyal2023-11-141-2/+3
* drm/i915: Bump GLK CDCLK frequency when driving multiple pipesVille Syrjälä2023-11-041-0/+12
* drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late()Imre Deak2023-09-281-1/+1
* drm/i915/lnl: Start using CDCLK through PLLStanislav Lisovskiy2023-09-211-2/+7
* drm/i915/lnl: Add CDCLK tableStanislav Lisovskiy2023-09-211-1/+29
* drm/i915/xe2lpd: Extend Wa_15010685871Lucas De Marchi2023-09-211-3/+4
* drm/i915/display: Eliminate IS_METEORLAKE checksMatt Roper2023-08-211-2/+2
* drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlckAnkit Nautiyal2023-08-181-14/+45
* drm/i915/rplu: s/ADLP_RPLU/RAPTORLAKE_U in RPLU definesDnyaneshwar Bhadane2023-08-071-1/+1
* drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics stepDnyaneshwar Bhadane2023-08-071-1/+1
* drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane2023-08-071-2/+2
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