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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
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* drm/i915/dpio: Extract bxt_dpio_phy_regs.hVille Syrjälä2024-04-191-0/+1
* drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glkVille Syrjälä2024-04-191-1/+1
* drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä2024-04-171-63/+120
* drm/i915: Pass the PLL hw_state to pll->enable()Ville Syrjälä2024-04-171-32/+37
* drm/i915: Introduce some local PLL state variablesVille Syrjälä2024-04-171-40/+50
* drm/i915: Rename PLL hw_state variables/argumentsVille Syrjälä2024-04-171-111/+112
* drm/i915/display: use intel_encoder_is/to_* functionsJani Nikula2024-03-211-15/+7
* drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed()Jonathon Hall2024-03-181-1/+1
* drm/i915: Convert intel_dpll_dump_hw_state() to drm_printerVille Syrjälä2024-03-151-58/+47
* drm/i915: Add PLL .compare_hw_state() vfuncVille Syrjälä2024-02-151-0/+95
* drm/i915: Reuse ibx_dump_hw_state() for gmch platformsVille Syrjälä2024-02-151-7/+1
* drm/i915: Convert PLL flags to booleansVille Syrjälä2024-01-261-10/+9
* drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLsVille Syrjälä2024-01-261-4/+19
* drm/i915: Include the PLL name in the debug messagesVille Syrjälä2024-01-261-19/+20
* drm/i915: Try to preserve the current shared_dpll for fastset on type-c portsVille Syrjälä2024-01-231-1/+7
* drm/i915: Replace a memset() with zero initializationVille Syrjälä2024-01-191-3/+1
* drm/i915: Stop printing pipe name as hexVille Syrjälä2023-11-241-1/+1
* drm/i915: Extract _intel_{enable,disable}_shared_dpll()Ville Syrjälä2023-10-311-14/+23
* drm/i915: Move the DPLL extra power domain handling up one levelVille Syrjälä2023-10-311-6/+10
* drm/i915: Abstract the extra JSL/EHL DPLL4 power domain betterVille Syrjälä2023-10-311-22/+8
* drm/i915: Use named initializers for DPLL infoVille Syrjälä2023-10-311-63/+67
* drm/i915: Simplify DPLL state checker calling conventionVille Syrjälä2023-10-061-5/+9
* drm/i915: Constify the crtc states in the DPLL checkerVille Syrjälä2023-10-061-3/+3
* drm/i915: s/dev_priv/i915/ in the shared_dpll codeVille Syrjälä2023-10-041-440/+440
* drm/i915: Introduce for_each_shared_dpll()Ville Syrjälä2023-10-041-21/+17
* drm/i915: Decouple I915_NUM_PLLS from PLL IDsVille Syrjälä2023-10-041-2/+24
* drm/i915: Stop requiring PLL index == PLL IDVille Syrjälä2023-10-041-27/+36
* Merge tag 'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drmLinus Torvalds2023-08-301-12/+17
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| * drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics stepDnyaneshwar Bhadane2023-08-071-1/+1
| * drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane2023-08-071-10/+15
| * drm/i915/hsw: s/HSW/HASWELL for platform/subplatform definesDnyaneshwar Bhadane2023-08-071-1/+1
* | drm/i915: Move abs_diff() to math.hAndy Shevchenko2023-08-181-0/+1
|/
* drm/i915: Make the CRTC state consistent during sanitize-disablingImre Deak2023-05-161-1/+1
* drm/i915: Add helpers to reference/unreference a DPLL for a CRTCImre Deak2023-05-161-12/+46
* drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula2023-05-151-14/+16
* drm/i915/dpll: drop a useless I915_STATE_WARN_ON()Jani Nikula2023-05-151-2/+0
* drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada2023-04-141-1/+1
* drm/i915/display/dpll: use intel_de_rmw if possibleAndrzej Hajda2023-02-161-112/+53
* drm/i915: move pch_ssc_use to display sub-struct under dpllJani Nikula2023-01-181-2/+2
* drm/i915/hti: abstract hti handlingJani Nikula2022-11-171-9/+2
* drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula2022-11-111-0/+1
* drm/i915/tgl+: Sanitize DKL PHY register definitionsImre Deak2022-10-261-24/+24
* drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.hImre Deak2022-10-261-0/+1
* drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.hImre Deak2022-10-261-1/+1
* drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak2022-10-261-32/+27
* drm/i915: Nuke intel_get_shared_dpll_id()Ville Syrjälä2022-09-261-22/+0
* drm/i915: Always initialize dpll.lockVille Syrjälä2022-09-261-1/+2
* drm/i915: WARN if PLL ref/unref got messed upVille Syrjälä2022-09-261-1/+6
* drm/i915: Pimp DPLL ref/unref debugsVille Syrjälä2022-09-261-3/+8
* drm/i915: Drop pointless 'budget' variableVille Syrjälä2022-09-261-16/+6
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