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path: root/drivers/gpu/drm/i915/display/intel_dsb.c
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* drm/i915/dsb: Add i915.enable_dsb module parameterVille Syrjälä2024-06-201-0/+3
* drm/i915/dsb: Convert the DSB code to use intel_display rather than i915Ville Syrjälä2024-06-201-26/+26
* drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare()Ville Syrjälä2024-06-201-4/+7
* drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()Ville Syrjälä2024-06-051-2/+4
* drm/i915/dsb: Move DSB ID definition to the headerVille Syrjälä2024-06-051-8/+0
* drm/i915/dsb: Polish the DSB ID enumVille Syrjälä2024-06-051-11/+11
* drm/i915: drop unnecessary i915_reg.h includesJani Nikula2024-05-311-1/+0
* drm/i915: Reuse intel_mode_vblank_start()Ville Syrjälä2024-05-311-7/+3
* drm/i915/dsb: Always set DSB_SKIP_WAITS_ENVille Syrjälä2024-03-071-2/+3
* drm/i915/dsb: Fix DSB vblank waits when using VRRVille Syrjälä2024-03-071-0/+14
* drm/i915/lnl: Program PKGC_LATENCY registerSuraj Kandpal2024-02-231-1/+1
* drm/i915: Disable DSB in Xe KMDJosé Roberto de Souza2024-01-051-0/+4
* drm/i915: correct the input parameter on _intel_dsb_commit()heminhong2023-11-291-1/+1
* drm/i915/dsb: DSB code refactoringAnimesh Manna2023-11-161-62/+36
* drm/i915/dsb: Correct DSB command buffer cache coherency settingsVille Syrjälä2023-10-131-4/+11
* drm/i915/dsb: Allocate command buffer from local memoryVille Syrjälä2023-10-131-1/+6
* drm/i915/dsb: Use DEwake to combat PkgC latencyVille Syrjälä2023-09-271-12/+79
* drm/i915/dsb: Add support for non-posted DSB registers writesVille Syrjälä2023-09-271-0/+20
* drm/i915/dsb: Introduce intel_dsb_reg_write_masked()Ville Syrjälä2023-09-271-0/+18
* drm/i915/dsb: Introduce intel_dsb_noop()Ville Syrjälä2023-09-271-0/+9
* drm/i915/dsb: Define the contents of some intstructions bit betterVille Syrjälä2023-09-271-4/+8
* drm/i915/dsb: Use non-locked register accessVille Syrjälä2023-09-271-9/+9
* drm/i915/dsb: Don't use indexed writes when byte enables are not all setVille Syrjälä2023-09-071-3/+9
* drm/i915/dsb: Avoid corrupting the first register writeVille Syrjälä2023-09-071-0/+8
* drm/i915/dsb: Dump the DSB command buffer when DSB failsVille Syrjälä2023-09-071-3/+30
* drm/i915/dsb: split out DSB regs to a separate fileJani Nikula2023-03-301-0/+1
* drm/i915/dsb: Nuke the DSB debugVille Syrjälä2023-02-201-5/+0
* drm/i915/dsb: Allow vblank synchronized DSB executionVille Syrjälä2023-02-201-1/+3
* drm/i915/dsb: Introduce intel_dsb_finish()Ville Syrjälä2023-02-031-4/+7
* drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()Ville Syrjälä2023-02-031-2/+9
* drm/i915/dsb: Pimp debug/error printsVille Syrjälä2023-02-031-4/+8
* drm/i915/dsb: Add mode DSB opcodesVille Syrjälä2023-01-131-0/+8
* drm/i915/dsb: Allow the caller to pass in the DSB buffer sizeVille Syrjälä2023-01-131-15/+25
* drm/i915/dsb: Introduce intel_dsb_align_tail()Ville Syrjälä2023-01-131-6/+18
* drm/i915/dsb: Handle the indexed vs. not inside the DSB codeVille Syrjälä2023-01-131-56/+34
* drm/i915/dsb: Improve the indexed reg write checksVille Syrjälä2023-01-131-3/+18
* drm/i915/dsb: Extract intel_dsb_emit()Ville Syrjälä2023-01-131-10/+20
* drm/i915/dsb: Extract assert_dsb_has_room()Ville Syrjälä2023-01-131-10/+12
* drm/i915/dsb: Fix DSB command buffer size checksVille Syrjälä2023-01-131-2/+2
* drm/i915/dsb: Align DSB register writes to 8 bytesVille Syrjälä2023-01-131-0/+3
* drm/i915/dsb: Inline DSB_CTRL writes into intel_dsb_commit()Ville Syrjälä2023-01-131-48/+14
* drm/i915/dsb: Stop with the RMWVille Syrjälä2023-01-131-15/+7
* drm/i915: Make DSB lower levelVille Syrjälä2022-12-131-43/+39
* drm/i915: Move the DSB->mmio fallback into the LUT codeVille Syrjälä2022-12-131-15/+3
* drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula2022-11-111-0/+1
* drm/i915/dsb: hide struct intel_dsb betterJani Nikula2022-09-091-0/+30
* drm/i915/dsb: modified to drm_info in dsb_prepare()Animesh Manna2022-04-051-3/+4
* drm/i915: split out i915_gem_internal.h from i915_drv.hJani Nikula2022-02-111-0/+2
* drm/i915: Use unlocked register accesses for LUT loadsVille Syrjälä2021-11-101-2/+2
* drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä2021-05-051-0/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-31 17:16:30 +0000