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path: root/drivers/gpu/drm/i915/display/skl_watermark.c
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* drm/i915: Plumb the full atomic state into skl_ddb_add_affected_planes()Ville Syrjälä2024-05-311-10/+9
* drm/i915: Handle SKL+ WM/DDB registers next to all other plane registersVille Syrjälä2024-05-151-93/+2
* drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()Ville Syrjälä2024-05-151-35/+22
* drm/i915: Extract skl_plane_{wm,ddb}_reg_val()Ville Syrjälä2024-05-151-10/+19
* drm/i915: Move skl+ wm/ddb registers to proper headersVille Syrjälä2024-05-151-0/+1
* drm/i915: Extract skl_universal_plane_regs.hVille Syrjälä2024-05-151-0/+1
* drm/i915/xe2hpd: Do not program MBUS_DBOX BW creditsJosé Roberto de Souza2024-05-031-1/+1
* drm/i915: Reject async flips if we need to change DDB/watermarksVille Syrjälä2024-05-031-0/+12
* drm/i915/display: Disable SAGV on bw init, to force QGV point recalculationStanislav Lisovskiy2024-04-191-1/+1
* drm/i915: move i915_fixed.h to display/intel_fixed.hJani Nikula2024-04-081-1/+1
* drm/i915: Optimize out redundant dbuf slice updatesVille Syrjälä2024-04-041-9/+18
* drm/i915: Use a plain old int for the cdclk/mdclk ratioVille Syrjälä2024-04-041-2/+4
* drm/i915: Implement vblank synchronized MBUS join changesStanislav Lisovskiy2024-04-041-36/+86
* drm/i915: Use the correct mdclk/cdclk ratio in MBUS updatesVille Syrjälä2024-04-041-11/+8
* drm/i915: Add debugs for mbus joining and dbuf ratio programmingVille Syrjälä2024-04-041-0/+9
* drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()Ville Syrjälä2024-04-041-18/+25
* drm/i915: Extract intel_dbuf_mbus_join_update()Ville Syrjälä2024-04-041-11/+24
* drm/i915: Relocate intel_mbus_dbox_update()Ville Syrjälä2024-04-041-83/+83
* drm/i915: Loop over all active pipes in intel_mbus_dbox_updateStanislav Lisovskiy2024-04-041-6/+1
* drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changesGustavo Sousa2024-03-131-8/+32
* drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_stateGustavo Sousa2024-03-131-1/+17
* drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()Gustavo Sousa2024-03-131-11/+19
* drm/i915/lnl: Program PKGC_LATENCY registerSuraj Kandpal2024-02-231-2/+52
* drm/i915: Compute use_sagv_wm differentlyVille Syrjälä2024-02-021-15/+23
* Revert "drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation"Ville Syrjälä2024-01-221-9/+7
* drm/i915/display: Move enable_sagv module parameter under displayJouni Högander2023-10-261-2/+3
* drm/i915: Simplify watermark state checker calling conventionVille Syrjälä2023-10-071-3/+5
* drm/i915: Constify watermark state checkerVille Syrjälä2023-10-071-1/+1
* drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late()Imre Deak2023-09-281-1/+1
* drm/i915: Introduce skl_watermark_max_latency()Ville Syrjälä2023-09-271-0/+14
* drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocationStanislav Lisovskiy2023-09-211-7/+9
* drm/i915: annotate maybe unused but set intel_crtc_state variablesJani Nikula2023-06-071-1/+1
* drm/i915: Convert INTEL_INFO()->display to a pointerMatt Roper2023-05-241-4/+4
* drm/i915/wm: split out SKL+ watermark regs to a separate fileJani Nikula2023-04-041-0/+1
* drm/i915/psr: Implement Display WA #1136Jouni Högander2023-03-311-5/+0
* drm/i915/psr: Implement Wa_14015648006Jouni Högander2023-03-311-2/+5
* drm/i915: Add i915.enable_sagv modparamVille Syrjälä2023-03-251-0/+4
* drm/i915: Reject wm levels that exceed vblank timeVille Syrjälä2023-03-101-2/+116
* drm/i915: Extract skl_wm_latency()Ville Syrjälä2023-03-101-14/+26
* drm/i915: remove unnecessary intel_pm.h includesJani Nikula2023-03-061-1/+0
* drm/i915: Copy highest enabled wm level to disabled wm levels for gen >= 9Stanislav Lisovskiy2023-02-161-11/+15
* drm/i915/wm: add .get_hw_state to watermark funcsJani Nikula2023-02-151-2/+9
* drm/i915/wm: move remaining watermark code out of intel_pm.cJani Nikula2023-02-151-5/+6
* drm/i915: Replace wm.max_levels with wm.num_levels and use it everywhereVille Syrjälä2023-02-101-32/+30
* drm/i915: Populate wm.max_level for everyoneVille Syrjälä2023-02-101-0/+5
* drm/i915: Expose SAGV state via debugfsVille Syrjälä2023-02-011-5/+26
* drm/i915: Introduce HAS_SAGV()Ville Syrjälä2023-02-011-3/+3
* drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabledVille Syrjälä2023-02-011-1/+2
* drm/i915: implement async_flip mode per plane trackingAndrzej Hajda2023-01-301-0/+4
* drm/i915/wm: switch to intel_de_* register accessors in display codeJani Nikula2022-12-081-24/+18
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-31 20:49:09 +0000