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path: root/drivers/gpu/drm/i915/i915_irq.c
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* drm/i915: vlv: sanitize RPS interrupt mask during GPU idlingImre Deak2015-01-121-1/+3
* drm/i915: fix HW lockup due to missing RPS IRQ workaround on GEN6Imre Deak2015-01-121-2/+16
* drm/i915: Don't call intel_prepare_page_flip() multiple times on gen2-4Ville Syrjälä2014-12-181-4/+2
* drm/i915: move RPS PM_IER enabling to gen6_enable_rps_interruptsImre Deak2014-12-151-3/+13
* drm/i915: vlv: fix IRQ masking when uninstalling interruptsImre Deak2014-12-111-1/+1
* drm/i915: mask RPS IRQs properly when disabling RPSImre Deak2014-12-031-7/+20
* drm/i915: Tune down spurious CRC interrupt warningDaniel Vetter2014-12-031-1/+1
* drm/i915: Grab modeset locks for GPU rest on pre-ctgVille Syrjälä2014-12-031-1/+4
* drm/i915: Stop gathering error states for CS error interruptsDaniel Vetter2014-12-031-18/+7
* drm/i915: Only call mod_timer() if not already pendingChris Wilson2014-11-201-3/+4
* drm/i915: Remove DRI1 ring accessors and APIChris Wilson2014-11-191-6/+0
* drm/i915: sanitize rps irq disablingImre Deak2014-11-191-7/+16
* drm/i915: sanitize rps irq enablingImre Deak2014-11-191-1/+13
* drm/i915: WARN if we receive any rps interrupts on gen>9Imre Deak2014-11-191-3/+3
* drm/i915: Don't continually defer the hangcheckChris Wilson2014-11-191-3/+6
* drm/i915: Use vlv display irq setup code for chvVille Syrjälä2014-11-141-35/+2
* drm/i915: Refactor vlv_display_irq_uninstall()Ville Syrjälä2014-11-141-10/+15
* drm/i915/skl: AUX irqs have movedJesse Barnes2014-11-141-4/+13
* drm/i915: WARN if we receive any gen9 rps interruptsImre Deak2014-11-141-0/+5
* drm/i915: move rps irq enable/disable to i915_irq.cImre Deak2014-11-141-0/+41
* drm/i915: unify gen6/gen8 rps irq handlerImre Deak2014-11-141-14/+6
* drm/i915: unify gen6/gen8 pm irq helpersImre Deak2014-11-141-49/+10
* drm/i915: Make mmio flip wait for seqno in the work functionAnder Conselvan de Oliveira2014-11-071-3/+0
* drm/i915: Kill leftover GTIIR writes from valleyview_irq_preinstall()Ville Syrjälä2014-11-071-4/+0
* drm/i915: Drop useless VLV_IIR writes from vlv_display_irq_postinstall()Ville Syrjälä2014-11-071-3/+0
* drm/i914: Refactor vlv_display_irq_postinstall()Ville Syrjälä2014-11-071-3/+8
* drm/i915: Refactor vlv_display_irq_reset()Ville Syrjälä2014-11-071-23/+17
* drm/i915: Make valleyview_display_irqs_(un)install() work for chvVille Syrjälä2014-11-071-10/+17
* drm/i915: Call gen5_gt_irq_reset() from valleyview_irq_uninstall()Ville Syrjälä2014-11-071-0/+2
* drm/i915: Use GEN5_IRQ_RESET() on vlv/chvVille Syrjälä2014-11-071-20/+5
* drm/i915: Use a consistent order between IIR, IER, IMR writes on vlv/chvVille Syrjälä2014-11-071-11/+18
* drm/i915: Drop the extra GEN8_PCU_IIR posting read from cherryview_irq_preins...Ville Syrjälä2014-11-071-2/+0
* drm/i915: Use gen8_gt_irq_reset() in cherryview_irq_uninstall()Ville Syrjälä2014-11-071-26/+2
* drm/i915: Use DPINVGTT_STATUS_MASKVille Syrjälä2014-11-071-1/+1
* drm/i915: Apply some ocd for IMR vs. IER order during irq enableVille Syrjälä2014-11-071-4/+4
* drm/i915: Filter gmch fifo underruns in the shared handlerDaniel Vetter2014-10-241-3/+3
* drm/i915: Add wrappers to handle fifo underrun interruptsDaniel Vetter2014-10-241-51/+21
* drm/i915: Use dev_priv in public intel_fifo_underrun.c functionsDaniel Vetter2014-10-241-13/+22
* drm/i915: Extract intel_fifo_underrun.cDaniel Vetter2014-10-241-292/+5
* Merge branch 'drm-intel-next-fixes' into drm-intel-nextDaniel Vetter2014-10-211-30/+11
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| * drm/i915: fix short vs. long hpd detectionJani Nikula2014-10-161-7/+7
| * drm/i915: properly reenable gen8 pipe IRQsPaulo Zanoni2014-10-081-2/+3
| * Revert "drm/i915/bdw: BDW Software Turbo"Daniel Vetter2014-09-291-21/+0
* | drm/i915: kerneldoc for interrupt enable/disable functionsDaniel Vetter2014-10-031-2/+59
* | drm/i915: Use dev_priv instead of dev in irq setup functionsDaniel Vetter2014-10-031-22/+18
* | drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/Daniel Vetter2014-10-031-5/+21
* | drm/i915: Bikeshed rpm functions name a bit.Daniel Vetter2014-10-011-3/+3
* | Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter2014-09-301-11/+30
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| * | drm/i915/skl: Adjust the display engine interruptsDamien Lespiau2014-09-241-9/+28
| * | drm/i915/skl: SKL shares the same underrun interrupt as BDWDamien Lespiau2014-09-241-1/+1
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