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path: root/drivers/gpu/drm/i915/intel_dsi_pll.c
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* drm/i915/dsi: rename the current DSI files based on first platformJani Nikula2018-07-061-650/+0
* drm/i915/glk: Validate only DSI PORT A PLL dividerMadhav Chauhan2017-02-281-6/+13
* drm/i915/glk: Program txesc clock divider for GLKDeepak M2017-02-281-2/+59
* drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXTDeepak M2017-02-281-10/+15
* drm/i915/glk: Add DSI PLL divider range for glkDeepak M2017-02-281-7/+17
* drm/i915: Fix PLL 8x/3 divider for MIPI video modeUma Shankar2017-02-151-5/+1
* drm/i915: relax uncritical udelay_range()Nicholas Mc Guire2016-12-161-2/+4
* drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira2016-12-021-6/+6
* drm/i915: Make IS_BROXTON only take dev_privTvrtko Ursulin2016-10-141-13/+13
* drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson2016-07-041-6/+6
* drm/i915: Fix buffer overflow in dsi_calc_mnp()Chris Wilson2016-07-021-8/+9
* drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson2016-06-301-1/+5
* drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson2016-06-301-2/+5
* drm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()Ville Syrjälä2016-04-151-22/+6
* drm/i915: Compute DSI PLL parameters during .compute_config()Ville Syrjälä2016-04-151-70/+86
* drm/i915: Fix CHV DSI PLL refclk during state readoutVille Syrjälä2016-04-121-1/+1
* drm/i915: Power down the DSI PLL before reconfiguring itVille Syrjälä2016-04-121-8/+0
* drm/i915: Change lfsr_converts[] to u16Ville Syrjälä2016-04-121-1/+1
* drm/i915/bxt: Fix DSI HW state readoutImre Deak2016-03-241-0/+40
* drm/i915/dsi: start using enum mipi_dsi_pixel_formatJani Nikula2016-03-161-25/+5
* drm/i915/dsi: lose the loose 666 format name in favor of packedJani Nikula2016-03-161-2/+2
* drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwardsDeepak M2016-03-031-17/+39
* drm/i915/dsi: Using the bpp value wrt the pixel formatDeepak M2016-02-191-1/+1
* drm/i915/dsi: remove unused dsi_rr_formula()Jani Nikula2016-01-081-81/+0
* drm/i915/dsi: abstract get pclk platform differencesJani Nikula2016-01-081-2/+10
* drm/i915: Separate cherryview from valleyviewWayne Boyer2015-12-101-3/+3
* drm/i915/bxt: vlv_dsi_reset_clocks() can be statickbuild test robot2015-10-061-2/+2
* drm/i915/bxt: get DSI pixelclockShashank Sharma2015-10-021-0/+35
* drm/i915/bxt: DSI disable and post-disableShashank Sharma2015-10-021-0/+39
* drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma2015-10-021-0/+42
* drm/i915/bxt: Disable DSI PLL for BXTShashank Sharma2015-09-231-1/+31
* drm/i915/bxt: Enable BXT DSI PLLShashank Sharma2015-09-231-1/+94
* drm/i915: Changes required to enable DSI Video Mode on CHTGaurav K Singh2015-07-031-6/+20
* drm/i915: Support for higher DSI clkGaurav K Singh2015-07-031-2/+2
* drm/i915/dsi: abstract dsi bpp derivation from pixel formatJani Nikula2015-07-031-43/+24
* drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä2015-05-281-7/+7
* drm/i915/dsi: add support for DSI PLL N1 divisor valuesJani Nikula2015-05-201-6/+11
* drm/i915: clean up dsi pll calculationJani Nikula2015-05-201-36/+17
* drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port CGaurav K Singh2014-12-101-2/+3
* drm/i915: cck reg used for checking DSI Pll lockedGaurav K Singh2014-12-051-2/+4
* drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual linkGaurav K Singh2014-12-051-0/+3
* drm/i915: Align intel_dsi*.c files a bitDaniel Vetter2014-08-081-4/+4
* drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar2014-08-081-6/+3
* drm/i915: Add correct hw/sw config check for DSI encoderShobhit Kumar2014-08-071-0/+81
* drm/i915: Try harder to get best m, n, p values with minimal errorShobhit Kumar2013-12-111-10/+20
* drm/i915: Compute dsi_clk from pixel clockShobhit Kumar2013-12-111-58/+31
* drm/i915: Use adjusted_mode in DSI PLL calculationsVille Syrjälä2013-09-161-2/+2
* drm/i915: add VLV DSI PLL Calculationsymohanma2013-09-041-0/+317
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