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path: root/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
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* drm/msm/dsi: Add phy configuration for MSM8937Daniil Titov2024-06-251-0/+18
* drm/msm/dsi: Remove dsi_phy_write_[un]delay()Konrad Dybcio2024-06-231-29/+52
* drm/msm/dsi: Remove dsi_phy_read/write()Konrad Dybcio2024-06-231-114/+110
* drm/msm/dsi: Add phy configuration for MSM8226Luca Weiss2023-06-041-0/+97
* drm/msm/dsi: Take advantage of devm_regulator_bulk_get_const()Douglas Anderson2022-09-181-18/+10
* drm/msm/dsi: Don't set a load before disabling a regulatorDouglas Anderson2022-09-181-3/+3
* drm/msm/dsi_phy_28nm: Replace parent names with clk_hw pointersMarijn Suijten2022-09-181-27/+23
* drm/msm/dsi/phy: Replace hardcoded char-array length with sizeof()Marijn Suijten2022-09-181-12/+12
* drm/msm/dsi/phy: Reindent and reflow multiline function callsMarijn Suijten2022-09-181-37/+36
* drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parentMarijn Suijten2022-02-181-1/+3
* drm/msm: Generated register updateRob Clark2021-06-231-0/+1
* drm/msm/dsi: stop passing src_pll_id to the phy_enable callDmitry Baryshkov2021-04-071-2/+2
* drm/msm/dsi: inline msm_dsi_phy_set_src_pllDmitry Baryshkov2021-04-071-6/+7
* drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instancesDmitry Baryshkov2021-04-071-27/+21
* drm/msm/dsi: move ioremaps to dsi_phy_driver_probeDmitry Baryshkov2021-04-071-21/+12
* drm/msm/dsi: drop PLL accessor functionsDmitry Baryshkov2021-04-071-59/+59
* drm/msm/dsi: drop msm_dsi_pll abstractionDmitry Baryshkov2021-04-071-38/+45
* drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phyDmitry Baryshkov2021-04-071-20/+14
* drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepareDmitry Baryshkov2021-04-071-29/+57
* drm/msm/dsi: simplify vco_delay handling in dsi_phy_28nm driverDmitry Baryshkov2021-04-071-8/+4
* drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocksDmitry Baryshkov2021-04-071-28/+22
* drm/msm/dsi: push provided clocks handling into a generic codeDmitry Baryshkov2021-04-071-55/+8
* drm/msm/dsi: move min/max PLL rate to phy configDmitry Baryshkov2021-04-071-2/+6
* drm/msm/dsi: drop global msm_dsi_phy_type enumarationDmitry Baryshkov2021-04-071-11/+8
* drm/msm/dsi: move all PLL callbacks into PHY config structDmitry Baryshkov2021-04-071-22/+43
* drm/msm/dsi: drop multiple pll enable_seq supportDmitry Baryshkov2021-04-071-7/+16
* drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* codeDmitry Baryshkov2021-04-071-0/+637
* drm/msm/dsi: replace PHY's init callback with configurable dataDmitry Baryshkov2021-04-071-3/+3
* drm/msm/dsi: Add configuration for 28nm PLL on family BAngeloGioacchino Del Regno2019-11-041-0/+18
* drm/msm/dsi: Implement qcom, dsi-phy-regulator-ldo-mode for 28nm PHYStephan Gerhold2019-10-241-8/+34
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner2019-06-051-9/+1
* drm: msm: Use DRM_DEV_* instead of dev_*Mamta Shukla2018-12-111-1/+1
* drm/msm/dsi: Move PHY operations out of hostHai Li2017-02-061-2/+2
* drm/msm/dsi: Add a PHY op that initializes version specific stuffArchit Taneja2017-02-061-0/+2
* drm/msm/dsi: Don't get DSI index from DTArchit Taneja2016-07-161-0/+4
* drm/msm/dsi: Fix regulator API abuseArchit Taneja2016-05-081-2/+2
* drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHYHai Li2015-10-221-4/+2
* drm/msm/dsi: Split PHY drivers to separate filesHai Li2015-08-151-0/+166
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-10 14:55:19 +0000