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path: root/drivers/mmc/host/sdhci_am654.c
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* mmc: sdhci_am654: Constify struct regmap_configJavier Carrasco2024-07-081-1/+1
| | | | | | | | | `sdhci_am654_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Link: https://lore.kernel.org/r/20240705-sdhci_am654-const-regmap_config-v1-1-c166a8d48a66@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Constify struct sdhci_opsKrzysztof Kozlowski2024-04-261-3/+3
| | | | | | | | | The local struct sdhci_ops can be made const for code safety. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240414-mmc-const-sdhci-ops-v2-4-262f81faadac@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Update comments in sdhci_am654_set_clockJudith Mendez2024-04-021-2/+2
| | | | | | | | | | | The sdhci_am654_set_clock function is also used to enable delay chain, therefore fix comments to be more generic in case we are not enabling DLL. Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240320223837.959900-6-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Fix itapdly/otapdly array typeJudith Mendez2024-04-021-2/+2
| | | | | | | | | | While integer type works, the otap_del_sel and itap_del_sel arrays are manipulated as u32, so change array types to u32. Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240320223837.959900-5-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Fix ITAPDLY for HS400 timingJudith Mendez2024-04-021-0/+9
| | | | | | | | | | | | | | | | | | While STRB is currently used for DATA and CRC responses, the CMD responses from the device to the host still require ITAPDLY for HS400 timing. Currently what is stored for HS400 is the ITAPDLY from High Speed mode which is incorrect. The ITAPDLY for HS400 speed mode should be the same as ITAPDLY as HS200 timing after tuning is executed. Add the functionality to save ITAPDLY from HS200 tuning and save as HS400 ITAPDLY. Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed modes") Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240320223837.959900-8-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add ITAPDLYSEL in sdhci_j721e_4bit_set_clockJudith Mendez2024-04-021-3/+9
| | | | | | | | | | | | Add ITAPDLYSEL to sdhci_j721e_4bit_set_clock function. This allows to set the correct ITAPDLY for timings that do not carry out tuning. Fixes: 1accbced1c32 ("mmc: sdhci_am654: Add Support for 4 bit IP on J721E") Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240320223837.959900-7-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add OTAP/ITAP delay enableJudith Mendez2024-04-021-14/+26
| | | | | | | | | | | | | | | | | | Currently the OTAP/ITAP delay enable functionality is incorrect in the am654_set_clock function. The OTAP delay is not enabled when timing < SDR25 bus speed mode. The ITAP delay is not enabled for timings that do not carry out tuning. Add this OTAP/ITAP delay functionality according to the datasheet [1] OTAPDLYENA and ITAPDLYENA for MMC0. [1] https://www.ti.com/lit/ds/symlink/am62p.pdf Fixes: 8ee5fc0e0b3b ("mmc: sdhci_am654: Update OTAPDLY writes") Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240320223837.959900-4-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Write ITAPDLY for DDR52 timingJudith Mendez2024-04-021-0/+1
| | | | | | | | | | | | | For DDR52 timing, DLL is enabled but tuning is not carried out, therefore the ITAPDLY value in PHY CTRL 4 register is not correct. Fix this by writing ITAPDLY after enabling DLL. Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed modes") Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240320223837.959900-3-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add tuning algorithm for delay chainJudith Mendez2024-04-021-20/+92
| | | | | | | | | | | | | | | | | | | | | | | Currently the sdhci_am654 driver only supports one tuning algorithm which should be used only when DLL is enabled. The ITAPDLY is selected from the largest passing window and the buffer is viewed as a circular buffer. The new algorithm should be used when the delay chain is enabled. The ITAPDLY is selected from the largest passing window and the buffer is not viewed as a circular buffer. This implementation is based off of the following paper: [1]. Also add support for multiple failing windows. [1] https://www.ti.com/lit/an/spract9/spract9.pdf Fixes: 13ebeae68ac9 ("mmc: sdhci_am654: Add support for software tuning") Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240320223837.959900-2-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Drop lookup for deprecated ti,otap-del-selVignesh Raghavendra2023-12-071-31/+6
| | | | | | | | | | | | | ti,otap-del-sel has been deprecated since v5.7 and there are no users of this property and no documentation in the DT bindings either. Drop the fallback code looking for this property, this makes sdhci_am654_get_otap_delay() much easier to read as all the TAP values can be handled via a single iterator loop. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20231122060215.2074799-1-vigneshr@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: fix start loop index for TAP value parsingNitin Yadav2023-11-031-1/+1
| | | | | | | | | | | | | ti,otap-del-sel-legacy/ti,itap-del-sel-legacy passed from DT are currently ignored for all SD/MMC and eMMC modes. Fix this by making start loop index to MMC_TIMING_LEGACY. Fixes: 8ee5fc0e0b3b ("mmc: sdhci_am654: Update OTAPDLY writes") Signed-off-by: Nitin Yadav <n-yadav@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231026061458.1116276-1-n-yadav@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Convert to platform remove callback returning voidYangtao Li2023-08-151-3/+2
| | | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yangtao Li <frank.li@vivo.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230727070051.17778-60-frank.li@vivo.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Properly handle failures in .remove()Yangtao Li2023-08-151-4/+5
| | | | | | | | | | | | Returning an error code in a platform driver's remove function is wrong most of the time and there is an effort to make the callback return void. To prepare this rework the function not to exit early. Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yangtao Li <frank.li@vivo.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230727070051.17778-59-frank.li@vivo.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add support for PM suspend/resumeAswath Govindraju2023-04-041-16/+131
| | | | | | | | | | Add support for suspend/resume and pm_runtime resume/suspend. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230331101619.4117312-1-vigneshr@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Set HIGH_SPEED_ENA for SDR12 and SDR25Bhavya Kapoor2023-03-231-2/+0
| | | | | | | | | | | | | Timing Information in Datasheet assumes that HIGH_SPEED_ENA=1 should be set for SDR12 and SDR25 modes. But sdhci_am654 driver clears HIGH_SPEED_ENA register. Thus, Modify sdhci_am654 to not clear HIGH_SPEED_ENA (HOST_CONTROL[2]) bit for SDR12 and SDR25 speed modes. Fixes: e374e87538f4 ("mmc: sdhci_am654: Clear HISPD_ENA in some lower speed modes") Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230317092711.660897-1-b-kapoor@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: lower power-on failed message severityFrancesco Dolcini2023-03-091-1/+1
| | | | | | | | | | | | | | Lower the power-on failed message severity from warn to info when the controller does not power-up. It's normal to have this situation when the SD card slot is empty, therefore we should not warn the user about it. Fixes: 7ca0f166f5b2 ("mmc: sdhci_am654: Add workaround for card detect debounce timer") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230306162751.163369-1-francesco@dolcini.it Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Use dev_err_probe() for mmc_of_parse() return codeMatthias Schiffer2022-12-071-1/+1
| | | | | | | | | Checking phandle references like mmc-pwrseq can result in -EPROBE_DEFER. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20221101105242.2019036-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Fix SDHCI_RESET_ALL for CQHCIBrian Norris2022-11-071-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Engine to J721E") Signed-off-by: Brian Norris <briannorris@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20221026124150.v4.6.I35ca9d6220ba48304438b992a76647ca8e5b126f@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Remove the unneeded result variableye xingchen2022-09-141-4/+1
| | | | | | | | | | | Return the value cqhci_init() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20220830083349.276709-1-ye.xingchen@zte.com.cn Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* drivers: mmc: sdhci_am654: Add the quirk to set TESTCD bitVignesh Raghavendra2022-04-261-1/+22
| | | | | | | | | | | | | | | | The ARASAN MMC controller on Keystone 3 class of devices need the SDCD line to be connected for proper functioning. Similar to the issue pointed out in sdhci-of-arasan.c driver, commit 3794c542641f ("mmc: sdhci-of-arasan: Set controller to test mode when no CD bit"). In cases where this can't be connected, add a quirk to force the controller into test mode and set the TESTCD bit. Use the flag "ti,fails-without-test-cd", to implement this above quirk when required. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20220425063120.10135-3-a-govindraju@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add Support for TI's AM62 SoCAswath Govindraju2022-02-281-0/+4
| | | | | | | | | | | | | | | | | Add support for the controller present on the AM62x SoC. There are instances: sdhci0: 8bit bus width, max 200 MBps sdhci1: 4bit bus width, max 100 MBps sdhci2: 4bit bus width, max 100 MBps The PHY used for 8 bit instance is same as the PHY for the 4 bit instance. Therefore, introduce a new bus width independent compatible for AM62 SoC that uses the driver data required for 4 bit instance. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20220218072840.5629-1-a-govindraju@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Fix the driver data of AM64 SoCAswath Govindraju2022-02-281-22/+2
| | | | | | | | | | | The MMCSD IPs used in AM64 are the same as the ones used in J721E. Therefore, fix this by using the driver data from J721E for AM64 too, for both 8 and 4 bit instances. Fixes: 754b7f2f7d2a ("mmc: sdhci_am654: Add Support for TI's AM64 SoC") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20220211075056.26179-1-a-govindraju@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Use pm_runtime_resume_and_get() to replace open codingTian Tao2021-06-141-4/+2
| | | | | | | | | | use pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. this change is just to simplify the code, no actual functional changes. Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Link: https://lore.kernel.org/r/1621558775-31185-1-git-send-email-tiantao6@hisilicon.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: replace mmc->parent with mmc_dev() for consistencyJisheng Zhang2021-03-301-1/+1
| | | | | | | | | | | As pointed out by Ulf, "both "mmc->parent" and mmc_dev(mmc) are being used in the entire c-file". Convert all the mmc->parent usage in all sdhci host driver to mmc_dev() for consistency. Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20210324155013.1e5faa3c@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add Support for TI's AM64 SoCFaiz Abbas2021-02-011-0/+28
| | | | | | | | | | | | | | | Add support for the controller present on the AM64x SoC. There are instances: sdhci0: 8bit bus width, max 400 MBps sdhci1: 4bit bus width, max 100 MBps Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20210113115908.3882-3-a-govindraju@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Fix module autoloadFaiz Abbas2020-10-091-0/+1
| | | | | | | | | Add a MODULE_DEVICE_TABLE() entry so that the driver is autoloaded when built as a module. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20201008100129.13917-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Enable tuning for SDR50Faiz Abbas2020-09-281-0/+6
| | | | | | | | | | | | According to the SW tuning App note[1], tuning is required for all UHS speed modes. Tuning for SDR50 is not enabled in Capabilities by default so enable it from the CTL_CFG registers. [1] https://www.ti.com/lit/pdf/spract9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-7-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add support for software tuningFaiz Abbas2020-09-281-0/+41
| | | | | | | | | | | | | | | | | | With the new SW tuning App note[1], a custom tuning algorithm is required for eMMC HS200, HS400 and SD card UHS modes. The algorithm involves running through the 32 possible input tap delay values and sending the appropriate tuning command (CMD19/21) for each of them to get a fail or pass result for each of the values. Typically, the range will have a small contiguous failing window. Considering the tuning range as a circular buffer, the algorithm then sets a final tuned value directly opposite to the failing window. [1] https://www.ti.com/lit/pdf/spract9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-6-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add support for input tap delayFaiz Abbas2020-09-281-30/+84
| | | | | | | | | | | | | | | | DLL need only be enabled for speed modes and clock frequencies at or above 50 MHz. For speed modes that don't enable the DLL, we need to configure a static input delay value. This involves reading an optional itap-del-sel-* value from the device tree and configuring it for the appropriate speed mode. With this addition, make sure that DLL is always switched off at the beginning of the set_clock() call to simplify configuration. This also removes the need for the dll_on member in struct sdhci_am654_data. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-5-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Fix hard coded otap delay array sizeFaiz Abbas2020-09-281-21/+21
| | | | | | | | | Change hard coded array size value to depend on struct timing_data array size. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v5.4Douglas Anderson2020-09-071-0/+1
| | | | | | | | | | This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers. This batch converts the drivers that appeared to be around in the v5.4 timeframe. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200903162412.5.I2b630c4d40ff4ea61d5b30b8ccfe95890e257100@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add workaround for card detect debounce timerFaiz Abbas2020-09-071-0/+24
| | | | | | | | | | | | | | | There is a one time delay because of a card detect debounce timer in the controller IP. This timer runs as soon as power is applied to the module regardless of whether a card is present or not and any writes to SDHCI_POWER_ON will return 0 before it expires. This timeout has been measured to be about 1 second in am654x and j721e. Write-and-read-back in a loop on SDHCI_POWER_ON for a maximum of 1.5 seconds to make sure that the controller actually powers on. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200825170015.32285-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Replace HTTP links with HTTPS onesAlexander A. Klimov2020-09-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200718090614.88946-1-grandmaster@al2klimov.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add support for clkbuf_sel propertyFaiz Abbas2020-07-131-0/+11
| | | | | | | | | Add support for writing new clkbuf_sel property for the J721e 4 bit IP. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200619125801.9530-7-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Update delay chain configurationFaiz Abbas2020-07-131-1/+9
| | | | | | | | | For speed modes where DLL is not enabled write to TXDLYCLK to enable transmitter delay chain mode. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200619125801.9530-6-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Fix conditions for enabling dllFaiz Abbas2020-07-131-22/+20
| | | | | | | | | | | The clock > CLOCK_TOO_SLOW_HZ condition gating phy configuration is only required because dll should not be enabled at too low a clock frequency or too low timing. Make sure that this condition only gates dll enablement. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200619125801.9530-5-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add Support for SR2.0Faiz Abbas2020-07-131-1/+22
| | | | | | | | | Add Support for AM65x PG2.0. Use the SoC bus framework to fixup the driver data and skip do DLL calibration if the revision is 1.0 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200619125801.9530-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add flag for PHY calibrationFaiz Abbas2020-07-131-3/+5
| | | | | | | | | Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB flag to indicate the same. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200619125801.9530-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: am654: Use sdhci_set_power_and_voltage()Nicolas Saenz Julienne2020-03-241-14/+3
| | | | | | | | | | The sdhci core provides a helper function with the same functionality as this controller's set_power() callback. Use it instead. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200306174413.20634-8-nsaenzjulienne@suse.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Enable DLL only for some speed modesFaiz Abbas2020-03-241-60/+68
| | | | | | | | | | | Its recommended that DLL must only be enabled for SDR50, DDR50, DDR52, SDR104, HS200 and HS400 speed modes. Move DLL configuration to its own function and call it only in the above speed modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108150920.14547-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Update OTAPDLY writesFaiz Abbas2020-03-241-18/+105
| | | | | | | | | | | | | | | According to the latest AM65x Data Manual[1], a different output tap delay value is optimum for a given speed mode. Therefore, deprecate the ti,otap-del-sel binding and introduce a new binding for each of the possible MMC/SD speed modes. If the legacy mode is not found, fall back to old binding to maintain dts compatibility. [1] http://www.ti.com/lit/gpn/am6526 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108150920.14547-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* Merge branch 'fixes' into nextUlf Hansson2020-01-161-19/+35
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| * mmc: sdhci_am654: Fix Command Queuing in AM65xFaiz Abbas2020-01-161-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Command Queuing was enabled completely for J721e controllers which lead to partial enablement even for Am65x. Complete CQ implementation for AM65x by adding the irq callback. Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Engine to J721E") Cc: stable@vger.kernel.org Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108143301.1929-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci_am654: Reset Command and Data line after tuningFaiz Abbas2020-01-161-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | The tuning data is leftover in the buffer after tuning. This can cause issues in future data commands, especially with CQHCI. Reset the command and data lines after tuning to continue from a clean state. Fixes: 41fd4caeb00b ("mmc: sdhci_am654: Add Initial Support for AM654 SDHCI driver") Cc: stable@vger.kernel.org Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108143301.1929-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci_am654: Remove Inverted Write Protect flagFaiz Abbas2020-01-161-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC/SD controllers on am65x and j721e don't in fact detect the write protect line as inverted. No issues were detected because of this because the sdwp line is not connected on any of the evms. Fix this by removing the flag. Fixes: 1accbced1c32 ("mmc: sdhci_am654: Add Support for 4 bit IP on J721E") Cc: stable@vger.kernel.org Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108143301.1929-2-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | mmc: sdhci_am654: convert to devm_platform_ioremap_resourceYangtao Li2019-12-181-3/+1
|/ | | | | | | | Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Link: https://lore.kernel.org/r/20191215175120.3290-8-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add Support for Command Queuing Engine to J721EFaiz Abbas2019-11-201-1/+70
| | | | | | | | | | Add Support for CQHCI (Command Queuing Host Controller Interface) for each of the host controllers present in TI's J721E devices. Add cqhci_ops and a .irq() callback to handle cqhci specific interrupts. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Make some symbols staticYueHaibing2019-07-101-3/+4
| | | | | | | | | | | | Fix sparse warnings: drivers/mmc/host/sdhci_am654.c:192:6: warning: symbol 'sdhci_j721e_4bit_set_clock' was not declared. Should it be static? drivers/mmc/host/sdhci_am654.c:261:18: warning: symbol 'sdhci_j721e_8bit_ops' was not declared. Should it be static? drivers/mmc/host/sdhci_am654.c:284:18: warning: symbol 'sdhci_j721e_4bit_ops' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add Support for 4 bit IP on J721EFaiz Abbas2019-06-171-38/+86
| | | | | | | | | | | Add support for 4 bit instances on TI's J721E devices. Because these instances have no DLL, introduce a DLL_PRESENT flag and make sure DLL related registers are only accessed when it is present. Also add a separate set_clock callback for this compatible. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci_am654: Add Support for 8 bit IP on J721EFaiz Abbas2019-06-171-25/+110
| | | | | | | | | | | | | | | | | | | | | | | | The 8 bit IP on the TI's J721E device departs from the AM654x IP in some ways which require special handling. Create a driver_data structure which holds the pltfm_data and a flags field which is used to indicate these differences. These are the following: 1. The pins are not muxed with anything else inside the SoC and hence the IOMUX_ENABLE field does not exist. Add a flag which is used to indicate the presence of the field. 2. The register field used to select DLL frequency is 3 bit wide as compared to 2 bits in AM65x. Add another flag which differentiates between 3 bit and 2 bit fields. 3. The strobe select field is 8 bit wide as compared to 4 bits for AM65x. Add yet another flag to indicate this difference. Strobe select is used only for HS400 speed mode, support for which has not yet been added in AM65x. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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