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* Merge branch 'pci/yijing-mps-v8' into nextBjorn Helgaas2013-08-263-29/+45
|\ | | | | | | | | | | | | | | | | | | | | * pci/yijing-mps-v8: PCI: Warn if unsafe MPS settings detected PCI: Fix MPS peer-to-peer DMA comment syntax PCI: Don't restrict MPS for slots below Root Ports PCI: Simplify MPS test for Downstream Port PCI: Remove unnecessary check for pcie_get_mps() failure PCI: Simplify pcie_bus_configure_settings() interface PCI: Drop "PCI-E" prefix from Max Payload Size message
| * PCI: Warn if unsafe MPS settings detectedYijing Wang2013-08-261-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a BIOS configures MPS incorrectly, devices may not work normally. For example, if a bridge has MPS set larger than an endpoint below it, the endpoint may discard packets. To help diagnose this issue, print a warning if we find an endpoint MPS setting different than that of the upstream bridge. [bhelgaas: changelog, "bridge" temporary, warning text] Reference: https://bugzilla.kernel.org/show_bug.cgi?id=60799 Reported-by: Joe Jin <joe.jin@oracle.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jon Mason <jdmason@kudzu.us>
| * PCI: Fix MPS peer-to-peer DMA comment syntaxJon Mason2013-08-261-1/+1
| | | | | | | | | | | | | | Correct minor wording issue in MPS peer-to-peer comment. Noticed by Don Dutile. Signed-off-by: Jon Mason <jdmason@kudzu.us> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: Don't restrict MPS for slots below Root PortsYijing Wang2013-08-221-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting with "pci=pcie_bus_safe", we previously limited the fabric MPS to 128 when we found: (1) A hotplug-capable Downstream Port ("dev->is_hotplug_bridge && pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT"), or (2) A hotplug-capable Root Port with a slot that was either empty or contained a multi-function device ("dev->is_hotplug_bridge && !list_is_singular(&dev->bus->devices)") Part (1) is valid, but part (2) is not. After a hot-add in the slot below a Root Port, we can reconfigure all MPS values in the fabric below the Root Port because the new device is the only thing below the Root Port and there are no active drivers. Therefore, there's no reason to limit the MPS for Root Ports, no matter what's in the slot. Test info: -+-[0000:40]-+-07.0-[0000:46]--+-00.0 Intel 82576 NIC \-00.1 Intel 82576 NIC 0000:40:07.0 Root Port bridge to [bus 46] (MPS supported=256) 0000:46:00.0 Endpoint (MPS supported=512) 0000:46:00.1 Endpoint (MPS supported=512) # echo 0 > /sys/bus/pci/slots/7/power # echo 1 > /sys/bus/pci/slots/7/power pcieport 0000:40:07.0: PCI-E Max Payload Size set to 256/ 256 (was 256) pci 0000:46:00.0: PCI-E Max Payload Size set to 256/ 512 (was 128) pci 0000:46:00.1: PCI-E Max Payload Size set to 256/ 512 (was 128) Before this change, we set MPS to 128 for the Root Port and both NICs because the slot contained a multi-function device and dev->is_hotplug_bridge && !list_is_singular(&dev->bus->devices) was true. After this change, we set it to 256. [bhelgaas: changelog, comments, split out upstream bridge check] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jon Mason <jdmason@kudzu.us>
| * PCI: Simplify MPS test for Downstream PortBjorn Helgaas2013-08-221-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe hotplug bridges are always either Root Ports or Downstream Ports. No other device type can have a PCIe link leading downstream to a slot. Root Ports don't have an upstream bridge, so "dev->is_hotplug_bridge && dev->bus->self" is true if and only if "dev" is a Downstream Port. That means we can simplify this by looking at the type of "dev" itself, without looking upstream at all. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: Remove unnecessary check for pcie_get_mps() failureYijing Wang2013-08-221-3/+0
| | | | | | | | | | | | | | | | | | | | | | After 59875ae489 ("PCI/core: Use PCI Express Capability accessors"), pcie_get_mps() never returns an error, so don't bother to check for it. No functional change. [bhelgaas: changelog, fix pcie_get_mps() doc] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: Simplify pcie_bus_configure_settings() interfaceBjorn Helgaas2013-08-222-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on a patch by Jon Mason (see URL below). All users of pcie_bus_configure_settings() pass arguments of the form "bus, bus->self->pcie_mpss". The "mpss" argument is redundant since we can easily look it up internally. In addition, all callers check "bus->self" for NULL, which we can also do internally. This patch simplifies the interface and the callers. No functional change. Reference: http://lkml.kernel.org/r/1317048850-30728-2-git-send-email-mason@myri.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: Drop "PCI-E" prefix from Max Payload Size messageBjorn Helgaas2013-08-221-1/+1
| | | | | | | | | | | | | | The conventional spelling is "PCIe", but I think even that is superfluous, so remove the whole thing. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/yinghai-assign-unassigned-v6' into nextBjorn Helgaas2013-08-265-95/+97
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/yinghai-assign-unassigned-v6: PCI: Assign resources for hot-added host bridge more aggressively PCI: Move resource reallocation code to non-__init PCI: Delay enabling bridges until they're needed PCI: Assign resources on a per-bus basis PCI: Enable unassigned resource reallocation on per-bus basis PCI: Turn on reallocation for unassigned resources with host bridge offset PCI: Look for unassigned resources on per-bus basis PCI: Drop temporary variable in pci_assign_unassigned_resources()
| * | PCI: Assign resources for hot-added host bridge more aggressivelyYinghai Lu2013-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When hot-adding an ACPI host bridge, use pci_assign_unassigned_root_bus_resources() instead of pci_assign_unassigned_bus_resources(). The former is more aggressive and will release and reassign existing resources if necessary. This is safe at hot-add time because no drivers are bound to devices below the new host bridge yet. [bhelgaas: changelog, split __init changes out for reviewability] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Move resource reallocation code to non-__initYinghai Lu2013-07-251-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Resource reallocation is currently done only at boot-time, but will soon be done when host bridge is hot-added. This patch removes the __init annotations so the code will still be present after boot. [bhelgaas: split __init changes out] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Delay enabling bridges until they're neededYinghai Lu2013-07-255-28/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently enable PCI bridges after scanning a bus and assigning resources. This is often done in arch code. This patch changes this so we don't enable a bridge until necessary, i.e., until we enable a PCI device behind the bridge. We do this in the generic pci_enable_device() path, so this also removes the arch-specific code to enable bridges. [bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Assign resources on a per-bus basisYinghai Lu2013-07-251-37/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we did resource assignment globally. This patch splits up pci_assign_unassigned_resources() so assignment is done for each root bus in turn. We check each root bus individually to see whether it needs any reassignment, and if it does, we assign resources for just that bus. [bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Enable unassigned resource reallocation on per-bus basisYinghai Lu2013-07-251-19/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_realloc_detect() turns on automatic resource allocation when it finds unassigned SR-IOV resources. Previously it did this on a global basis, so we enabled reallocation if any PCI device anywhere had an unassigned SR-IOV resource. This patch changes pci_realloc_detect() so it looks at a single bus, so we can do this when a host bridge is hot-added. [bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Turn on reallocation for unassigned resources with host bridge offsetYinghai Lu2013-07-251-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we did not turn on automatic PCI resource reallocation for unassigned IOV resources behind a host bridge with address offset. This patch fixes that bug. The intent was that "!r->start" would check for a BAR containing zero. But that check is incorrect for host bridges that apply an offset, because in that case the resource address is not the same as the bus address. This patch fixes that by converting the resource address back to a bus address before checking for zero. [bhelgaas: changelog] Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Look for unassigned resources on per-bus basisYinghai Lu2013-07-251-15/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PCI_REALLOC_ENABLE_AUTO=y, pci_realloc_detect() looks at PCI devices to see if any have SR-IOV resources that need to be assigned. If it finds any, it turns on automatic resource reallocation. This patch changes pci_realloc_detect() so it uses pci_walk_bus() on each root bus instead of using for_each_pci_dev(). This is a step toward doing reallocation on a per-bus basis, so we can do it for a hot-added host bridge. [bhelgaas: changelog, rename callback to iov_resources_unassigned(), use boolean for "unassigned"] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Drop temporary variable in pci_assign_unassigned_resources()Yinghai Lu2013-07-251-10/+7
| |/ | | | | | | | | | | | | | | | | | | Drop the "bus" temporary variable. No functional change, but simplifies later patch slightly. [bhelgaas: changelog, make same change in pci_assign_unassigned_bridge_resources() to keep it parallel with pci_assign_unassigned_resources()] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/aw-reset-v5' into nextBjorn Helgaas2013-08-157-62/+393
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/aw-reset-v5: PCI: Add pci_probe_reset_slot() and pci_probe_reset_bus() PCI: Remove aer_do_secondary_bus_reset() PCI: Tune secondary bus reset timing PCI: Wake-up devices before saving config space for reset PCI: Add pci_reset_slot() and pci_reset_bus() PCI: Split out pci_dev lock/unlock and save/restore PCI: Add slot reset option to pci_dev_reset() PCI: pciehp: Add reset_slot() method PCI: Add hotplug_slot_ops.reset_slot() PCI: Add pci_reset_bridge_secondary_bus()
| * | PCI: Add pci_probe_reset_slot() and pci_probe_reset_bus()Alex Williamson2013-08-151-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | Users of pci_reset_bus() and pci_reset_slot() need a way to probe whether the bus or slot supports reset. Add trivial helper functions and export them as vfio-pci will make use of these. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Remove aer_do_secondary_bus_reset()Alex Williamson2013-08-143-36/+2
| | | | | | | | | | | | | | | | | | One PCI bus reset function to rule them all. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Tune secondary bus reset timingAlex Williamson2013-08-141-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI spec indicates that with stable power, reset needs to be asserted for a minimum of 1ms (Trst). We should be able to assume stable power for a Hot Reset, but we add another millisecond as a fudge factor to make sure the reset is seen on the bus for at least a full 1ms. After reset is de-asserted we must wait for devices to complete initialization. The specs refer to this as "recovery time" (Trhfa). For PCI this is 2^25 clock cycles or 2^26 for PCI-X. For minimum bus speeds, both of those come to 1s. PCIe "softens" this requirement with the Configuration Request Retry Status (CRS) completion status. Theoretically we could use CRS to shorten the wait time. We don't make use of that here, using a fixed 1s delay to allow devices to re-initialize. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Wake-up devices before saving config space for resetAlex Williamson2013-08-141-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devices come out of reset in D0. Restoring a device to a different post-reset state takes more smarts than our simple config space restore, which can leave devices in an inconsistent state. For example, if a device is reset in D3, but the restore doesn't successfully return the device to D3, then the actual state of the device and dev->current_state are contradictory. Put everything in D0 going into the reset, then we don't need to do anything special on the way out. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add pci_reset_slot() and pci_reset_bus()Alex Williamson2013-08-141-0/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes pci_reset_function() is not sufficient. We have cases where devices do not support any kind of reset, but there might be multiple functions on the bus preventing pci_reset_function() from doing a secondary bus reset. We also have cases where a device will advertise that it supports a PM reset, but really does nothing on D3hot->D0 (graphics cards are notorious for this). These devices often also have more than one function, so even blacklisting PM reset for them wouldn't allow a secondary bus reset through pci_reset_function(). If a driver supports multiple devices it should have the ability to induce a bus reset when it needs to. This patch provides that ability through pci_reset_slot() and pci_reset_bus(). It's the caller's responsibility when using these interfaces to understand that all of the devices in or below the slot (or on or below the bus) will be reset and therefore should be under control of the caller. PCI state of all the affected devices is saved and restored around these resets, but internal state of all of the affected devices is reset (which should be the intention). Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Split out pci_dev lock/unlock and save/restoreAlex Williamson2013-08-141-17/+38
| | | | | | | | | | | | | | | | | | | | | | | | Only cosmetic code changes to existing paths. Expand the comment in the new pci_dev_save_and_disable() function since there's a lot hidden in that Command register write. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add slot reset option to pci_dev_reset()Alex Williamson2013-08-141-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | If the hotplug controller provides a way to reset a slot, use that before a direct parent bus reset. Like the bus reset option, this is only available when a single pci_dev occupies the slot. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: pciehp: Add reset_slot() methodAlex Williamson2013-08-143-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe hotplug has a bus per slot, so we can just use a normal secondary bus reset. However, if a slot supports surprise removal, a bus reset can be seen as a presence detection change triggering a hot-remove followed by a hot-add. Disable presence detection from triggering an interrupt or being polled around the bus reset. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add pci_reset_bridge_secondary_bus()Alex Williamson2013-08-091-9/+23
| |/ | | | | | | | | | | | | | | Move the secondary bus reset code from pci_parent_bus_reset() into its own function. Export it as we'll later be calling it from hotplug controllers and elsewhere. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/vipul-chelsio-reset-v2' into nextBjorn Helgaas2013-08-122-29/+106
|\ \ | | | | | | | | | | | | | | | | | | | | | * pci/vipul-chelsio-reset-v2: PCI: Use pci_wait_for_pending_transaction() instead of for loop bnx2x: Use pci_wait_for_pending_transaction() instead of for loop PCI: Chelsio quirk: Enable Bus Master during Function-Level Reset PCI: Add pci_wait_for_pending_transaction()
| * | PCI: Use pci_wait_for_pending_transaction() instead of for loopCasey Leedom2013-08-121-16/+2
| | | | | | | | | | | | | | | | | | | | | | | | New routine has been added to avoid duplication of code to wait for pending PCI transactions to complete. This makes use of that function. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Chelsio quirk: Enable Bus Master during Function-Level ResetCasey Leedom2013-08-121-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4 can wedge if there are DMAs in flight within the chip and Bus Master has been disabled. We need to have it on till the Function Level Reset completes. T4 can also suffer a Head Of Line blocking problem if MSI-X interrupts are disabled before the FLR has completed. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add pci_wait_for_pending_transaction()Casey Leedom2013-08-121-13/+25
| |/ | | | | | | | | | | | | | | New routine to avoid duplication of code to wait for pending PCI transactions to complete. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/misc' into nextBjorn Helgaas2013-08-126-743/+874
|\ \ | | | | | | | | | | | | | | | | | | * pci/misc: PCI: exynos: Split into Synopsys part and Exynos part PCI: mvebu: Make Marvell PCIe driver depend on OF PCI: mvebu: Convert to use devm_ioremap_resource
| * | PCI: exynos: Split into Synopsys part and Exynos partJingoo Han2013-08-124-740/+869
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys Designware part; other parts are Exynos specific. Also, the Synopsys Designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys Designware part and Exynos specific part. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
| * | PCI: mvebu: Make Marvell PCIe driver depend on OFThomas Petazzoni2013-08-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell PCIe host controller driver is heavily tied to Device Tree APIs, and can only be used on platforms where the Device Tree is used. Therefore, it should "depends on OF" to avoid build failures on !OF configurations. Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: mvebu: Convert to use devm_ioremap_resourceTushar Behera2013-08-061-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 75096579c3ac ("lib: devres: Introduce devm_ioremap_resource()") introduced devm_ioremap_resource() and deprecated the use of devm_request_and_ioremap(). While at it, modify mvebu_pcie_map_registers() to propagate error code. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
* | | Merge branch 'pci/wei-resource-cleanups' into nextBjorn Helgaas2013-08-061-14/+11
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/wei-resource-cleanups: PCI: Align bridge I/O windows as required by downstream devices & bridges PCI: Fix types in pbus_size_io() PCI: Add comments for pbus_size_mem() parameters PCI: Enumerate subordinate buses, not devices, in pci_bus_get_depth()
| * | | PCI: Align bridge I/O windows as required by downstream devices & bridgesBjorn Helgaas2013-08-051-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An upstream bridge's I/O window must be at least as aligned as any downstream device or bridge requires. In particular, if the upstream bridge supports 1K alignment but a downstream bridge requires 4K alignment, the upstream window must also be 4K aligned. Therefore, do not reduce the required alignment ("min_align") based on the upstream bridge's capabilities. Reported-by: Wei Yang <weiyang@linux.vnet.ibm.com> Suggested-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | PCI: Fix types in pbus_size_io()Wei Yang2013-08-021-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the type of "size" to resource_size_t and makes the corresponding dev_printk() change. [bhelgaas: changelog] Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | PCI: Add comments for pbus_size_mem() parametersWei Yang2013-08-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fills in the missing description for two parameters of pbus_size_mem(). Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | PCI: Enumerate subordinate buses, not devices, in pci_bus_get_depth()Wei Yang2013-08-021-6/+3
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally, on one PCI bus there would be more devices than bridges. When calculating the depth of a PCI bus, it would be more time efficient to enumerating through the child buses instead of the child devices. Also by doing so, the code seems more self explaining. Previously, it went through the devices and checked whether a bridge introduced a child bus or not, which needs more background knowledge to understand it. This patch calculates the depth by enumerating the bus hierarchy. Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | | Merge branch 'pci/misc' into nextBjorn Helgaas2013-08-016-24/+39
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/misc: PCI: Fix comment typo for pci_add_cap_save_buffer() PCI: Return -ENOSYS for SR-IOV operations on non-SR-IOV devices PCI: Update NumVFs register when disabling SR-IOV x86/PCI: MMCONFIG: Check earlier for MMCONFIG region at address zero PCI: Convert class code to use dev_groups frv/PCI: Mark pcibios_fixup_bus() as non-init x86/pci/mrst: Cleanup checkpatch.pl warnings PCI: Rename "PCI Express support" kconfig title PCI: Fix comment typo in iov.c
| * | PCI: Fix comment typo for pci_add_cap_save_buffer()Yijing Wang2013-08-011-1/+1
| | | | | | | | | | | | | | | | | | Fix trivial comment typo for pci_add_cap_save_buffer(). Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Return -ENOSYS for SR-IOV operations on non-SR-IOV devicesStefan Assmann2013-07-311-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the return value to -ENOSYS if a device is not an SR-IOV PF. Previously we returned either -ENODEV or -EINVAL. Also have pci_sriov_get_totalvfs() return 0 in the error case to make the behaviour consistent whether CONFIG_PCI_IOV is enabled or not. Signed-off-by: Stefan Assmann <sassmann@kpanic.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Update NumVFs register when disabling SR-IOVYijing Wang2013-07-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we only update NumVFs register during sriov_enable(). This register should also be updated during sriov_disable() and when sriov_enable() fails. Otherwise, we will get the stale "Number of VFs" info from lspci. [bhelgaas: changelog] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Convert class code to use dev_groupsGreg Kroah-Hartman2013-07-253-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | The dev_attrs field of struct class is going away soon, dev_groups should be used instead. This converts the PCI class code to use the correct field. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Rename "PCI Express support" kconfig titleEzequiel Garcia2013-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous option title "PCI Express support" is confusing. The name seems to imply this option is required to get PCIe support, which is not true. Fix it to "PCI Express Port Bus support" which is more accurate. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Fix comment typo in iov.cJonghwan Choi2013-07-251-1/+1
| |/ | | | | | | | | | | "Devic3" should be "device." Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: Claim ACS support for AMD southbridge devicesAlex Williamson2013-07-251-0/+50
| | | | | | | | | | | | | | | | | | AMD confirmed that peer-to-peer between these devices is not possible. We can therefore claim that they support a subset of ACS. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Donald Dutile <ddutile@redhat.com>
* | PCI: Differentiate ACS controllable from enabledAlex Williamson2013-07-251-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently misinterpret that in order for an ACS feature to be enabled it must be set in the control field. In reality, this means that the feature is not only enabled, but controllable. Many of the ACS capability bits are not required if the device behaves by default in the way specified when both the capability and control bit are set and does not support or allow the alternate mode. We therefore need to check the capabilities and mask out flags that are enabled but not controllable. Egress control seems to be the only flag which is purely optional. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Donald Dutile <ddutile@redhat.com>
* | PCI: Check all ACS features for multifunction downstream portsAlex Williamson2013-07-251-14/+70
|/ | | | | | | | | | | | The multifunction ACS rules do not apply to downstream ports. Those should be tested regardless of whether they are single function or multifunction. The PCIe spec also fully specifies which PCIe types are subject to the multifunction rules and excludes event collectors and PCIe-to-PCI bridges entirely. Document each rule to the section of the PCIe spec and provide overall documentation of the function. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Donald Dutile <ddutile@redhat.com>
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