| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | MIPS: Loongson64: Rename CPU TYPES | Jiaxun Yang | 2019-10-31 | 1 | -1/+1 |
| * | drm: change func to better detect wether swiotlb is needed | Michael D Labriola | 2019-02-20 | 1 | -1/+1 |
| * | drm: disable uncached DMA optimization for ARM and arm64 | Ard Biesheuvel | 2019-02-06 | 1 | -0/+18 |
| * | drm: add func to get max iomem address v2 | Chunming Zhou | 2018-02-13 | 1 | -0/+2 |
| * | drm: Move drm_clflush prototypes to drm_cache header file | Gabriel Krisman Bertazi | 2017-01-10 | 1 | -0/+4 |
| * | drm: Loongson-3 doesn't fully support wc memory | Huacai Chen | 2016-04-22 | 1 | -0/+2 |
| * | drm: add helper to check for wc memory support | Dave Airlie | 2016-02-02 | 1 | -0/+9 |
| * | drm/ttm: consolidate cache flushing code in one place. | Dave Airlie | 2009-08-27 | 1 | -0/+38 |
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index : linux.git | |
| Linux kernel mainline tree | Linus Torvalds |
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