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* tools/testing/cxl: Require cache invalidation bypassDan Williams2022-12-051-0/+2
* Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams2022-12-051-2/+114
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| * tools/testing/cxl: Add XOR Math support to cxl_testAlison Schofield2022-12-031-3/+115
* | Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams2022-12-052-7/+407
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| * | tools/testing/cxl: add mechanism to lock mem device for testingDave Jiang2022-12-011-4/+44
| * | tools/testing/cxl: Add "passphrase secure erase" opcode supportDave Jiang2022-12-011-0/+102
| * | tools/testing/cxl: Add "Unlock" security opcode supportDave Jiang2022-12-011-0/+45
| * | tools/testing/cxl: Add "Freeze Security State" security opcode supportDave Jiang2022-12-011-0/+20
| * | tools/testing/cxl: Add "Disable" security opcode supportDave Jiang2022-12-011-0/+74
| * | tools/testing/cxl: Add "Set Passphrase" opcode supportDave Jiang2022-12-011-0/+88
| * | tools/testing/cxl: Add "Get Security State" opcode supportDave Jiang2022-12-011-7/+37
| * | cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operationDave Jiang2022-11-301-0/+1
* | | tools/testing/cxl: Add an RCH topologyDan Williams2022-12-052-11/+176
* | | cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter2022-12-034-0/+33
* | | tools/testing/cxl: Make mock CEDT parsing more robustDan Williams2022-12-021-4/+6
* | | cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams2022-12-021-3/+0
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* | tools/testing/cxl: Add bridge mocking supportDan Williams2022-11-141-2/+8
* | cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter2022-11-141-8/+1
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* tools/testing/cxl: Add a single-port host-bridge regression configDan Williams2022-11-041-19/+278
* tools/testing/cxl: Fix some error exitsDan Williams2022-11-041-2/+2
* cxl/hdm: Commit decoder state to hardwareDan Williams2022-07-251-0/+46
* cxl/region: Add region creation supportBen Widawsky2022-07-211-0/+1
* cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams2022-07-211-3/+7
* cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams2022-07-211-7/+16
* tools/testing/cxl: Fix decoder default stateDan Williams2022-07-101-1/+0
* tools/testing/cxl: Add partition supportDan Williams2022-07-102-63/+28
* tools/testing/cxl: Expand CFMWS windowsDan Williams2022-07-101-5/+5
* tools/testing/cxl: Move cxl_test resources to the top of memoryDan Williams2022-07-101-1/+2
* cxl/mem: Convert partition-info to resourcesDan Williams2022-07-091-1/+1
* cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams2022-07-091-1/+1
* tools/testing/cxl: Fix cxl_hdm_decode_init() calling conventionDan Williams2022-06-281-3/+5
* cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams2022-05-191-2/+3
* cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams2022-05-191-6/+3
* cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams2022-05-193-16/+5
* cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams2022-05-193-10/+17
* cxl/pci: Move cxl_await_media_ready() to the coreDan Williams2022-05-193-7/+16
* cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()Dan Williams2022-04-121-1/+1
* tools/testing/cxl: Add a physical_node linkDan Williams2022-02-081-2/+19
* tools/testing/cxl: Enumerate mock decodersDan Williams2022-02-081-20/+98
* tools/testing/cxl: Mock one level of switchesDan Williams2022-02-081-41/+97
* tools/testing/cxl: Fix root port to host bridge assignmentDan Williams2022-02-081-1/+1
* tools/testing/cxl: Mock dvsec_ranges()Dan Williams2022-02-081-0/+10
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-082-0/+16
* cxl/memdev: Add numa_node attributeDan Williams2022-02-081-0/+1
* cxl/pci: Emit device serial numberDan Williams2022-02-081-0/+1
* cxl/pci: Implement wait for media activeBen Widawsky2022-02-081-0/+8
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-083-30/+21
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-082-2/+5
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-084-0/+86
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-085-128/+71
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