blob: b24e5a202a48a549d05ff72e80cfe5822765065b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD2S90 Resolver-to-Digital Converter
maintainers:
- Matheus Tavares <matheus.bernardino@usp.br>
description: |
Datasheet: https://www.analog.com/en/products/ad2s90.html
properties:
compatible:
const: adi,ad2s90
reg:
maxItems: 1
spi-max-frequency:
maximum: 830000
description: |
Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
delay is expected between the application of a logic LO to CS and the
application of SCLK, as also specified. And since the delay is not
implemented in the spi code, to satisfy it, SCLK's period should be at
most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
roughly 830000Hz.
spi-cpol: true
spi-cpha: true
required:
- compatible
- reg
dependencies:
spi-cpol: [ spi-cpha ]
spi-cpha: [ spi-cpol ]
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
resolver@0 {
compatible = "adi,ad2s90";
reg = <0>;
spi-max-frequency = <830000>;
spi-cpol;
spi-cpha;
};
};
...
|
