1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
// SPDX-License-Identifier: GPL-2.0-only and MIT
/*
* Copyright 2024 NXP
*/
mipi1_subsys: bus@57220000 {
compatible = "simple-bus";
interrupt-parent = <&irqsteer_mipi1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x57220000 0x0 0x57220000 0x10000>;
irqsteer_mipi1: interrupt-controller@57220000 {
compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
reg = <0x57220000 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <1>;
clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_MIPI_1>;
fsl,channel = <0>;
fsl,num-irqs = <32>;
};
mipi1_lis_lpcg: clock-controller@57223000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x57223000 0x4>;
#clock-cells = <1>;
clocks = <&dsi_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mipi1_lis_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_MIPI_1>;
};
mipi1_pwm_lpcg: clock-controller@5722300c {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5722300c 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
<&dsi_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "mipi1_pwm_lpcg_clk",
"mipi1_pwm_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
};
mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5722301c 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mipi1_i2c0_lpcg_clk";
power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
};
mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x57223014 0x4>;
#clock-cells = <1>;
clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
};
mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x57223018 0x4>;
#clock-cells = <1>;
clocks = <&dsi_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
};
mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x57223024 0x4>;
#clock-cells = <1>;
clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
};
mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x57223028 0x4>;
#clock-cells = <1>;
clocks = <&dsi_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
};
mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5722302c 0x4>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "mipi1_i2c1_lpcg_clk";
power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
};
pwm_mipi1: pwm@57224000 {
compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
reg = <0x57224000 0x1000>;
clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
<&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <3>;
power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
status = "disabled";
};
i2c0_mipi1: i2c@57226000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x57226000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
interrupt-parent = <&irqsteer_mipi1>;
clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
<&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
clock-names = "per", "ipg";
assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
status = "disabled";
};
};
|
