1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019~2020, 2022 NXP
*/
/dts-v1/;
#include "imx8dxl.dtsi"
/ {
model = "Freescale i.MX8DXL EVK";
compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
aliases {
i2c2 = &i2c2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial6 = &cm40_lpuart;
};
chosen {
stdout-path = &lpuart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* Memory reserved for optee usage. Please do not use.
* This will be automatically added to dtb if OP-TEE is installed.
* optee@96000000 {
* reg = <0 0x96000000 0 0x2000000>;
* no-map;
* };
*/
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x14000000>;
alloc-ranges = <0 0x98000000 0 0x14000000>;
linux,cma-default;
};
};
m2_uart1_sel: regulator-m2uart1sel {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "m2_uart1_sel";
gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
mux3_en: regulator-0 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "mux3_en";
gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
regulator-always-on;
};
reg_fec1_sel: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "fec1_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
regulator-always-on;
status = "disabled";
};
reg_fec1_io: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "fec1_io_supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
status = "disabled";
};
reg_can0_stby: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "can0-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can1_stby: regulator-5 {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <3480>;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
mii_select: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "mii-select";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
&adc0 {
vref-supply = <®_vref_1v8>;
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
nvmem-cells = <&fec_mac1>;
nvmem-cell-names = "mac-address";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
eee-broken-1000t;
qca,disable-smarteee;
qca,disable-hibernation-mode;
reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <20>;
reset-deassert-us = <200000>;
vddio-supply = <&vddio0>;
vddio0: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
/*
* fec1 shares the some PINs with usdhc2.
* by default usdhc2 is enabled in this dts.
* Please disable usdhc2 to enable fec1
*/
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-txid";
phy-handle = <ðphy1>;
fsl,magic-packet;
rx-internal-delay-ps = <2000>;
nvmem-cells = <&fec_mac0>;
nvmem-cell-names = "mac-address";
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
qca,disable-smarteee;
vddio-supply = <&vddio1>;
vddio1: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
mt35xu512aba0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pca6416_1: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
pca6416_2: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
pca9548_1: i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
};
};
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pca6416_3: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&lsio_gpio2>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
};
pca9548_2: i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
};
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <®_can0_stby>;
status = "okay";
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan3>;
xceiver-supply = <®_can1_stby>;
status = "okay";
};
&cm40_intmux {
status = "disabled";
};
&cm40_lpuart {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cm40_lpuart>;
status = "disabled";
};
&lsio_gpio4 {
status = "okay";
};
&lsio_gpio5 {
status = "okay";
};
&thermal_zones {
pmic-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&usbphy1 {
/* USB eye diagram tests result */
fsl,tx-d-cal = <114>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
disable-over-current;
status = "okay";
};
&usbphy2 {
/* USB eye diagram tests result */
fsl,tx-d-cal = <111>;
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <®_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&lpspi3 {
fsl,spi-only-use-cs1-sel;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
>;
};
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021
IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021
>;
};
pinctrl_flexcan3: flexcan3grp {
fsl,pins = <
IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021
IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
>;
};
pinctrl_cm40_lpuart: cm40lpuartgrp {
fsl,pins = <
IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
>;
};
};
|